drm/mediatek/mtk_disp_rdma.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015 MediaTek Inc.
0004  */
0005
0006 #include <drm/drm_fourcc.h>
0007
0008 #include <linux/clk.h>
0009 #include <linux/component.h>
0010 #include <linux/module.h>
0011 #include <linux/of_device.h>
0012 #include <linux/of_irq.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/soc/mediatek/mtk-cmdq.h>
0016
0017 #include "mtk_disp_drv.h"
0018 #include "mtk_drm_crtc.h"
0019 #include "mtk_drm_ddp_comp.h"
0020
0021 #define DISP_REG_RDMA_INT_ENABLE        0x0000
0022 #define DISP_REG_RDMA_INT_STATUS        0x0004
0023 #define RDMA_TARGET_LINE_INT                BIT(5)
0024 #define RDMA_FIFO_UNDERFLOW_INT             BIT(4)
0025 #define RDMA_EOF_ABNORMAL_INT               BIT(3)
0026 #define RDMA_FRAME_END_INT              BIT(2)
0027 #define RDMA_FRAME_START_INT                BIT(1)
0028 #define RDMA_REG_UPDATE_INT             BIT(0)
0029 #define DISP_REG_RDMA_GLOBAL_CON        0x0010
0030 #define RDMA_ENGINE_EN                  BIT(0)
0031 #define RDMA_MODE_MEMORY                BIT(1)
0032 #define DISP_REG_RDMA_SIZE_CON_0        0x0014
0033 #define RDMA_MATRIX_ENABLE              BIT(17)
0034 #define RDMA_MATRIX_INT_MTX_SEL             GENMASK(23, 20)
0035 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB        (6 << 20)
0036 #define DISP_REG_RDMA_SIZE_CON_1        0x0018
0037 #define DISP_REG_RDMA_TARGET_LINE       0x001c
0038 #define DISP_RDMA_MEM_CON           0x0024
0039 #define MEM_MODE_INPUT_FORMAT_RGB565            (0x000 << 4)
0040 #define MEM_MODE_INPUT_FORMAT_RGB888            (0x001 << 4)
0041 #define MEM_MODE_INPUT_FORMAT_RGBA8888          (0x002 << 4)
0042 #define MEM_MODE_INPUT_FORMAT_ARGB8888          (0x003 << 4)
0043 #define MEM_MODE_INPUT_FORMAT_UYVY          (0x004 << 4)
0044 #define MEM_MODE_INPUT_FORMAT_YUYV          (0x005 << 4)
0045 #define MEM_MODE_INPUT_SWAP             BIT(8)
0046 #define DISP_RDMA_MEM_SRC_PITCH         0x002c
0047 #define DISP_RDMA_MEM_GMC_SETTING_0     0x0030
0048 #define DISP_REG_RDMA_FIFO_CON          0x0040
0049 #define RDMA_FIFO_UNDERFLOW_EN              BIT(31)
0050 #define RDMA_FIFO_PSEUDO_SIZE(bytes)            (((bytes) / 16) << 16)
0051 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes)     ((bytes) / 16)
0052 #define RDMA_FIFO_SIZE(rdma)            ((rdma)->data->fifo_size)
0053 #define DISP_RDMA_MEM_START_ADDR        0x0f00
0054
0055 #define RDMA_MEM_GMC                0x40402020
0056
0057 struct mtk_disp_rdma_data {
0058     unsigned int fifo_size;
0059 };
0060
0061 /*
0062  * struct mtk_disp_rdma - DISP_RDMA driver structure
0063  * @data: local driver data
0064  */
0065 struct mtk_disp_rdma {
0066     struct clk          *clk;
0067     void __iomem            *regs;
0068     struct cmdq_client_reg      cmdq_reg;
0069     const struct mtk_disp_rdma_data *data;
0070     void                (*vblank_cb)(void *data);
0071     void                *vblank_cb_data;
0072     u32             fifo_size;
0073 };
0074
0075 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
0076 {
0077     struct mtk_disp_rdma *priv = dev_id;
0078
0079     /* Clear frame completion interrupt */
0080     writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
0081
0082     if (!priv->vblank_cb)
0083         return IRQ_NONE;
0084
0085     priv->vblank_cb(priv->vblank_cb_data);
0086
0087     return IRQ_HANDLED;
0088 }
0089
0090 static void rdma_update_bits(struct device *dev, unsigned int reg,
0091                  unsigned int mask, unsigned int val)
0092 {
0093     struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
0094     unsigned int tmp = readl(rdma->regs + reg);
0095
0096     tmp = (tmp & ~mask) | (val & mask);
0097     writel(tmp, rdma->regs + reg);
0098 }
0099
0100 void mtk_rdma_register_vblank_cb(struct device *dev,
0101                  void (*vblank_cb)(void *),
0102                  void *vblank_cb_data)
0103 {
0104     struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
0105
0106     rdma->vblank_cb = vblank_cb;
0107     rdma->vblank_cb_data = vblank_cb_data;
0108 }
0109
0110 void mtk_rdma_unregister_vblank_cb(struct device *dev)
0111 {
0112     struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
0113
0114     rdma->vblank_cb = NULL;
0115     rdma->vblank_cb_data = NULL;
0116 }
0117
0118 void mtk_rdma_enable_vblank(struct device *dev)
0119 {
0120     rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
0121              RDMA_FRAME_END_INT);
0122 }
0123
0124 void mtk_rdma_disable_vblank(struct device *dev)
0125 {
0126     rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
0127 }
0128
0129 int mtk_rdma_clk_enable(struct device *dev)
0130 {
0131     struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
0132
0133     return clk_prepare_enable(rdma->clk);
0134 }
0135
0136 void mtk_rdma_clk_disable(struct device *dev)
0137 {
0138     struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
0139
0140     clk_disable_unprepare(rdma->clk);
0141 }
0142
0143 void mtk_rdma_start(struct device *dev)
0144 {
0145     rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
0146              RDMA_ENGINE_EN);
0147 }
0148
0149 void mtk_rdma_stop(struct device *dev)
0150 {
0151     rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
0152 }
0153
0154 void mtk_rdma_config(struct device *dev, unsigned int width,
0155              unsigned int height, unsigned int vrefresh,
0156              unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
0157 {
0158     unsigned int threshold;
0159     unsigned int reg;
0160     struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
0161     u32 rdma_fifo_size;
0162
0163     mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,
0164                DISP_REG_RDMA_SIZE_CON_0, 0xfff);
0165     mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,
0166                DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
0167
0168     if (rdma->fifo_size)
0169         rdma_fifo_size = rdma->fifo_size;
0170     else
0171         rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
0172
0173     /*
0174      * Enable FIFO underflow since DSI and DPI can't be blocked.
0175      * Keep the FIFO pseudo size reset default of 8 KiB. Set the
0176      * output threshold to 70% of max fifo size to make sure the
0177      * threhold will not overflow
0178      */
0179     threshold = rdma_fifo_size * 7 / 10;
0180     reg = RDMA_FIFO_UNDERFLOW_EN |
0181           RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
0182           RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
0183     mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);
0184 }
0185
0186 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
0187                      unsigned int fmt)
0188 {
0189     /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
0190      * is defined in mediatek HW data sheet.
0191      * The alphabet order in XXX is no relation to data
0192      * arrangement in memory.
0193      */
0194     switch (fmt) {
0195     default:
0196     case DRM_FORMAT_RGB565:
0197         return MEM_MODE_INPUT_FORMAT_RGB565;
0198     case DRM_FORMAT_BGR565:
0199         return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
0200     case DRM_FORMAT_RGB888:
0201         return MEM_MODE_INPUT_FORMAT_RGB888;
0202     case DRM_FORMAT_BGR888:
0203         return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
0204     case DRM_FORMAT_RGBX8888:
0205     case DRM_FORMAT_RGBA8888:
0206         return MEM_MODE_INPUT_FORMAT_ARGB8888;
0207     case DRM_FORMAT_BGRX8888:
0208     case DRM_FORMAT_BGRA8888:
0209         return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
0210     case DRM_FORMAT_XRGB8888:
0211     case DRM_FORMAT_ARGB8888:
0212         return MEM_MODE_INPUT_FORMAT_RGBA8888;
0213     case DRM_FORMAT_XBGR8888:
0214     case DRM_FORMAT_ABGR8888:
0215         return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
0216     case DRM_FORMAT_UYVY:
0217         return MEM_MODE_INPUT_FORMAT_UYVY;
0218     case DRM_FORMAT_YUYV:
0219         return MEM_MODE_INPUT_FORMAT_YUYV;
0220     }
0221 }
0222
0223 unsigned int mtk_rdma_layer_nr(struct device *dev)
0224 {
0225     return 1;
0226 }
0227
0228 void mtk_rdma_layer_config(struct device *dev, unsigned int idx,
0229                struct mtk_plane_state *state,
0230                struct cmdq_pkt *cmdq_pkt)
0231 {
0232     struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
0233     struct mtk_plane_pending_state *pending = &state->pending;
0234     unsigned int addr = pending->addr;
0235     unsigned int pitch = pending->pitch & 0xffff;
0236     unsigned int fmt = pending->format;
0237     unsigned int con;
0238
0239     con = rdma_fmt_convert(rdma, fmt);
0240     mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);
0241
0242     if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
0243         mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,
0244                    DISP_REG_RDMA_SIZE_CON_0,
0245                    RDMA_MATRIX_ENABLE);
0246         mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
0247                    &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0,
0248                    RDMA_MATRIX_INT_MTX_SEL);
0249     } else {
0250         mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,
0251                    DISP_REG_RDMA_SIZE_CON_0,
0252                    RDMA_MATRIX_ENABLE);
0253     }
0254     mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,
0255                   DISP_RDMA_MEM_START_ADDR);
0256     mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,
0257                   DISP_RDMA_MEM_SRC_PITCH);
0258     mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,
0259               DISP_RDMA_MEM_GMC_SETTING_0);
0260     mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,
0261                DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
0262
0263 }
0264
0265 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
0266                   void *data)
0267 {
0268     return 0;
0269
0270 }
0271
0272 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
0273                  void *data)
0274 {
0275 }
0276
0277 static const struct component_ops mtk_disp_rdma_component_ops = {
0278     .bind   = mtk_disp_rdma_bind,
0279     .unbind = mtk_disp_rdma_unbind,
0280 };
0281
0282 static int mtk_disp_rdma_probe(struct platform_device *pdev)
0283 {
0284     struct device *dev = &pdev->dev;
0285     struct mtk_disp_rdma *priv;
0286     struct resource *res;
0287     int irq;
0288     int ret;
0289
0290     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0291     if (!priv)
0292         return -ENOMEM;
0293
0294     irq = platform_get_irq(pdev, 0);
0295     if (irq < 0)
0296         return irq;
0297
0298     priv->clk = devm_clk_get(dev, NULL);
0299     if (IS_ERR(priv->clk)) {
0300         dev_err(dev, "failed to get rdma clk\n");
0301         return PTR_ERR(priv->clk);
0302     }
0303
0304     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0305     priv->regs = devm_ioremap_resource(dev, res);
0306     if (IS_ERR(priv->regs)) {
0307         dev_err(dev, "failed to ioremap rdma\n");
0308         return PTR_ERR(priv->regs);
0309     }
0310 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0311     ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
0312     if (ret)
0313         dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
0314 #endif
0315
0316     if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) {
0317         ret = of_property_read_u32(dev->of_node,
0318                        "mediatek,rdma-fifo-size",
0319                        &priv->fifo_size);
0320         if (ret) {
0321             dev_err(dev, "Failed to get rdma fifo size\n");
0322             return ret;
0323         }
0324     }
0325
0326     /* Disable and clear pending interrupts */
0327     writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE);
0328     writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
0329
0330     ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
0331                    IRQF_TRIGGER_NONE, dev_name(dev), priv);
0332     if (ret < 0) {
0333         dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
0334         return ret;
0335     }
0336
0337     priv->data = of_device_get_match_data(dev);
0338
0339     platform_set_drvdata(pdev, priv);
0340
0341     pm_runtime_enable(dev);
0342
0343     ret = component_add(dev, &mtk_disp_rdma_component_ops);
0344     if (ret) {
0345         pm_runtime_disable(dev);
0346         dev_err(dev, "Failed to add component: %d\n", ret);
0347     }
0348
0349     return ret;
0350 }
0351
0352 static int mtk_disp_rdma_remove(struct platform_device *pdev)
0353 {
0354     component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
0355
0356     pm_runtime_disable(&pdev->dev);
0357
0358     return 0;
0359 }
0360
0361 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
0362     .fifo_size = SZ_4K,
0363 };
0364
0365 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
0366     .fifo_size = SZ_8K,
0367 };
0368
0369 static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
0370     .fifo_size = 5 * SZ_1K,
0371 };
0372
0373 static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
0374     .fifo_size = 1920,
0375 };
0376
0377 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
0378     { .compatible = "mediatek,mt2701-disp-rdma",
0379       .data = &mt2701_rdma_driver_data},
0380     { .compatible = "mediatek,mt8173-disp-rdma",
0381       .data = &mt8173_rdma_driver_data},
0382     { .compatible = "mediatek,mt8183-disp-rdma",
0383       .data = &mt8183_rdma_driver_data},
0384     { .compatible = "mediatek,mt8195-disp-rdma",
0385       .data = &mt8195_rdma_driver_data},
0386     {},
0387 };
0388 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
0389
0390 struct platform_driver mtk_disp_rdma_driver = {
0391     .probe      = mtk_disp_rdma_probe,
0392     .remove     = mtk_disp_rdma_remove,
0393     .driver     = {
0394         .name   = "mediatek-disp-rdma",
0395         .owner  = THIS_MODULE,
0396         .of_match_table = mtk_disp_rdma_driver_dt_match,
0397     },
0398 };