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0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/io.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/module.h>
0011 #include <linux/mod_devicetable.h>
0012 #include <linux/platform_device.h>
0013
0014 #include "mtk_cec.h"
0015
0016 #define TR_CONFIG 0x00
0017 #define CLEAR_CEC_IRQ BIT(15)
0018
0019 #define CEC_CKGEN 0x04
0020 #define CEC_32K_PDN BIT(19)
0021 #define PDN BIT(16)
0022
0023 #define RX_EVENT 0x54
0024 #define HDMI_PORD BIT(25)
0025 #define HDMI_HTPLG BIT(24)
0026 #define HDMI_PORD_INT_EN BIT(9)
0027 #define HDMI_HTPLG_INT_EN BIT(8)
0028
0029 #define RX_GEN_WD 0x58
0030 #define HDMI_PORD_INT_32K_STATUS BIT(26)
0031 #define RX_RISC_INT_32K_STATUS BIT(25)
0032 #define HDMI_HTPLG_INT_32K_STATUS BIT(24)
0033 #define HDMI_PORD_INT_32K_CLR BIT(18)
0034 #define RX_INT_32K_CLR BIT(17)
0035 #define HDMI_HTPLG_INT_32K_CLR BIT(16)
0036 #define HDMI_PORD_INT_32K_STA_MASK BIT(10)
0037 #define RX_RISC_INT_32K_STA_MASK BIT(9)
0038 #define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
0039 #define HDMI_PORD_INT_32K_EN BIT(2)
0040 #define RX_INT_32K_EN BIT(1)
0041 #define HDMI_HTPLG_INT_32K_EN BIT(0)
0042
0043 #define NORMAL_INT_CTRL 0x5C
0044 #define HDMI_HTPLG_INT_STA BIT(0)
0045 #define HDMI_PORD_INT_STA BIT(1)
0046 #define HDMI_HTPLG_INT_CLR BIT(16)
0047 #define HDMI_PORD_INT_CLR BIT(17)
0048 #define HDMI_FULL_INT_CLR BIT(20)
0049
0050 struct mtk_cec {
0051 void __iomem *regs;
0052 struct clk *clk;
0053 int irq;
0054 bool hpd;
0055 void (*hpd_event)(bool hpd, struct device *dev);
0056 struct device *hdmi_dev;
0057 spinlock_t lock;
0058 };
0059
0060 static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
0061 unsigned int bits)
0062 {
0063 void __iomem *reg = cec->regs + offset;
0064 u32 tmp;
0065
0066 tmp = readl(reg);
0067 tmp &= ~bits;
0068 writel(tmp, reg);
0069 }
0070
0071 static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
0072 unsigned int bits)
0073 {
0074 void __iomem *reg = cec->regs + offset;
0075 u32 tmp;
0076
0077 tmp = readl(reg);
0078 tmp |= bits;
0079 writel(tmp, reg);
0080 }
0081
0082 static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
0083 unsigned int val, unsigned int mask)
0084 {
0085 u32 tmp = readl(cec->regs + offset) & ~mask;
0086
0087 tmp |= val & mask;
0088 writel(tmp, cec->regs + offset);
0089 }
0090
0091 void mtk_cec_set_hpd_event(struct device *dev,
0092 void (*hpd_event)(bool hpd, struct device *dev),
0093 struct device *hdmi_dev)
0094 {
0095 struct mtk_cec *cec = dev_get_drvdata(dev);
0096 unsigned long flags;
0097
0098 spin_lock_irqsave(&cec->lock, flags);
0099 cec->hdmi_dev = hdmi_dev;
0100 cec->hpd_event = hpd_event;
0101 spin_unlock_irqrestore(&cec->lock, flags);
0102 }
0103
0104 bool mtk_cec_hpd_high(struct device *dev)
0105 {
0106 struct mtk_cec *cec = dev_get_drvdata(dev);
0107 unsigned int status;
0108
0109 status = readl(cec->regs + RX_EVENT);
0110
0111 return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
0112 }
0113
0114 static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
0115 {
0116 mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
0117 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
0118 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
0119 mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
0120 HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
0121 RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
0122 }
0123
0124 static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
0125 {
0126 mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
0127 }
0128
0129 static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
0130 {
0131 mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
0132 }
0133
0134 static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
0135 {
0136 mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
0137 mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
0138 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
0139 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
0140 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
0141 usleep_range(5, 10);
0142 mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
0143 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
0144 mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
0145 mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
0146 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
0147 }
0148
0149 static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
0150 {
0151 void (*hpd_event)(bool hpd, struct device *dev);
0152 struct device *hdmi_dev;
0153 unsigned long flags;
0154
0155 spin_lock_irqsave(&cec->lock, flags);
0156 hpd_event = cec->hpd_event;
0157 hdmi_dev = cec->hdmi_dev;
0158 spin_unlock_irqrestore(&cec->lock, flags);
0159
0160 if (hpd_event)
0161 hpd_event(hpd, hdmi_dev);
0162 }
0163
0164 static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
0165 {
0166 struct device *dev = arg;
0167 struct mtk_cec *cec = dev_get_drvdata(dev);
0168 bool hpd;
0169
0170 mtk_cec_clear_htplg_irq(cec);
0171 hpd = mtk_cec_hpd_high(dev);
0172
0173 if (cec->hpd != hpd) {
0174 dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
0175 cec->hpd, hpd);
0176 cec->hpd = hpd;
0177 mtk_cec_hpd_event(cec, hpd);
0178 }
0179 return IRQ_HANDLED;
0180 }
0181
0182 static int mtk_cec_probe(struct platform_device *pdev)
0183 {
0184 struct device *dev = &pdev->dev;
0185 struct mtk_cec *cec;
0186 struct resource *res;
0187 int ret;
0188
0189 cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
0190 if (!cec)
0191 return -ENOMEM;
0192
0193 platform_set_drvdata(pdev, cec);
0194 spin_lock_init(&cec->lock);
0195
0196 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0197 cec->regs = devm_ioremap_resource(dev, res);
0198 if (IS_ERR(cec->regs)) {
0199 ret = PTR_ERR(cec->regs);
0200 dev_err(dev, "Failed to ioremap cec: %d\n", ret);
0201 return ret;
0202 }
0203
0204 cec->clk = devm_clk_get(dev, NULL);
0205 if (IS_ERR(cec->clk)) {
0206 ret = PTR_ERR(cec->clk);
0207 dev_err(dev, "Failed to get cec clock: %d\n", ret);
0208 return ret;
0209 }
0210
0211 cec->irq = platform_get_irq(pdev, 0);
0212 if (cec->irq < 0)
0213 return cec->irq;
0214
0215 ret = devm_request_threaded_irq(dev, cec->irq, NULL,
0216 mtk_cec_htplg_isr_thread,
0217 IRQF_SHARED | IRQF_TRIGGER_LOW |
0218 IRQF_ONESHOT, "hdmi hpd", dev);
0219 if (ret) {
0220 dev_err(dev, "Failed to register cec irq: %d\n", ret);
0221 return ret;
0222 }
0223
0224 ret = clk_prepare_enable(cec->clk);
0225 if (ret) {
0226 dev_err(dev, "Failed to enable cec clock: %d\n", ret);
0227 return ret;
0228 }
0229
0230 mtk_cec_htplg_irq_init(cec);
0231 mtk_cec_htplg_irq_enable(cec);
0232
0233 return 0;
0234 }
0235
0236 static int mtk_cec_remove(struct platform_device *pdev)
0237 {
0238 struct mtk_cec *cec = platform_get_drvdata(pdev);
0239
0240 mtk_cec_htplg_irq_disable(cec);
0241 clk_disable_unprepare(cec->clk);
0242 return 0;
0243 }
0244
0245 static const struct of_device_id mtk_cec_of_ids[] = {
0246 { .compatible = "mediatek,mt8173-cec", },
0247 {}
0248 };
0249 MODULE_DEVICE_TABLE(of, mtk_cec_of_ids);
0250
0251 struct platform_driver mtk_cec_driver = {
0252 .probe = mtk_cec_probe,
0253 .remove = mtk_cec_remove,
0254 .driver = {
0255 .name = "mediatek-cec",
0256 .of_match_table = mtk_cec_of_ids,
0257 },
0258 };
