drm/mcde/mcde_drm.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (C) 2018 Linus Walleij <linus.walleij@linaro.org>
0004  * Parts of this file were based on the MCDE driver by Marcus Lorentzon
0005  * (C) ST-Ericsson SA 2013
0006  */
0007 #include <drm/drm_simple_kms_helper.h>
0008
0009 #ifndef _MCDE_DRM_H_
0010 #define _MCDE_DRM_H_
0011
0012 /* Shared basic registers */
0013 #define MCDE_CR 0x00000000
0014 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
0015 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
0016 #define MCDE_CR_IFIFOCTRLEN BIT(15)
0017 #define MCDE_CR_UFRECOVERY_MODE_V422 BIT(16)
0018 #define MCDE_CR_WRAP_MODE_V422_SHIFT BIT(17)
0019 #define MCDE_CR_AUTOCLKG_EN BIT(30)
0020 #define MCDE_CR_MCDEEN BIT(31)
0021
0022 #define MCDE_CONF0 0x00000004
0023 #define MCDE_CONF0_SYNCMUX0 BIT(0)
0024 #define MCDE_CONF0_SYNCMUX1 BIT(1)
0025 #define MCDE_CONF0_SYNCMUX2 BIT(2)
0026 #define MCDE_CONF0_SYNCMUX3 BIT(3)
0027 #define MCDE_CONF0_SYNCMUX4 BIT(4)
0028 #define MCDE_CONF0_SYNCMUX5 BIT(5)
0029 #define MCDE_CONF0_SYNCMUX6 BIT(6)
0030 #define MCDE_CONF0_SYNCMUX7 BIT(7)
0031 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12
0032 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
0033 #define MCDE_CONF0_OUTMUX0_SHIFT 16
0034 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
0035 #define MCDE_CONF0_OUTMUX1_SHIFT 19
0036 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
0037 #define MCDE_CONF0_OUTMUX2_SHIFT 22
0038 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
0039 #define MCDE_CONF0_OUTMUX3_SHIFT 25
0040 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
0041 #define MCDE_CONF0_OUTMUX4_SHIFT 28
0042 #define MCDE_CONF0_OUTMUX4_MASK 0x70000000
0043
0044 #define MCDE_SSP 0x00000008
0045 #define MCDE_AIS 0x00000100
0046 #define MCDE_IMSCERR 0x00000110
0047 #define MCDE_RISERR 0x00000120
0048 #define MCDE_MISERR 0x00000130
0049 #define MCDE_SISERR 0x00000140
0050
0051 enum mcde_flow_mode {
0052     /* One-shot mode: flow stops after one frame */
0053     MCDE_COMMAND_ONESHOT_FLOW,
0054     /* Command mode with tearing effect (TE) IRQ sync */
0055     MCDE_COMMAND_TE_FLOW,
0056     /*
0057      * Command mode with bus turn-around (BTA) and tearing effect
0058      * (TE) IRQ sync.
0059      */
0060     MCDE_COMMAND_BTA_TE_FLOW,
0061     /* Video mode with tearing effect (TE) sync IRQ */
0062     MCDE_VIDEO_TE_FLOW,
0063     /* Video mode with the formatter itself as sync source */
0064     MCDE_VIDEO_FORMATTER_FLOW,
0065     /* DPI video with the formatter itsels as sync source */
0066     MCDE_DPI_FORMATTER_FLOW,
0067 };
0068
0069 struct mcde {
0070     struct drm_device drm;
0071     struct device *dev;
0072     struct drm_panel *panel;
0073     struct drm_bridge *bridge;
0074     struct drm_connector *connector;
0075     struct drm_simple_display_pipe pipe;
0076     struct mipi_dsi_device *mdsi;
0077     bool dpi_output;
0078     s16 stride;
0079     enum mcde_flow_mode flow_mode;
0080     unsigned int flow_active;
0081     spinlock_t flow_lock; /* Locks the channel flow control */
0082
0083     void __iomem *regs;
0084
0085     struct clk *mcde_clk;
0086     struct clk *lcd_clk;
0087     struct clk *hdmi_clk;
0088     /* Handles to the clock dividers for FIFO A and B */
0089     struct clk *fifoa_clk;
0090     struct clk *fifob_clk;
0091     /* Locks the MCDE FIFO control register A and B */
0092     spinlock_t fifo_crx1_lock;
0093
0094     struct regulator *epod;
0095     struct regulator *vana;
0096 };
0097
0098 #define to_mcde(dev) container_of(dev, struct mcde, drm)
0099
0100 static inline bool mcde_flow_is_video(struct mcde *mcde)
0101 {
0102     return (mcde->flow_mode == MCDE_VIDEO_TE_FLOW ||
0103         mcde->flow_mode == MCDE_VIDEO_FORMATTER_FLOW);
0104 }
0105
0106 bool mcde_dsi_irq(struct mipi_dsi_device *mdsi);
0107 void mcde_dsi_te_request(struct mipi_dsi_device *mdsi);
0108 void mcde_dsi_enable(struct drm_bridge *bridge);
0109 void mcde_dsi_disable(struct drm_bridge *bridge);
0110 extern struct platform_driver mcde_dsi_driver;
0111
0112 void mcde_display_irq(struct mcde *mcde);
0113 void mcde_display_disable_irqs(struct mcde *mcde);
0114 int mcde_display_init(struct drm_device *drm);
0115
0116 int mcde_init_clock_divider(struct mcde *mcde);
0117
0118 #endif /* _MCDE_DRM_H_ */