drm/lima/lima_pmu.c

0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
0003
0004 #include <linux/iopoll.h>
0005 #include <linux/device.h>
0006
0007 #include "lima_device.h"
0008 #include "lima_pmu.h"
0009 #include "lima_regs.h"
0010
0011 #define pmu_write(reg, data) writel(data, ip->iomem + reg)
0012 #define pmu_read(reg) readl(ip->iomem + reg)
0013
0014 static int lima_pmu_wait_cmd(struct lima_ip *ip)
0015 {
0016     struct lima_device *dev = ip->dev;
0017     int err;
0018     u32 v;
0019
0020     err = readl_poll_timeout(ip->iomem + LIMA_PMU_INT_RAWSTAT,
0021                  v, v & LIMA_PMU_INT_CMD_MASK,
0022                  100, 100000);
0023     if (err) {
0024         dev_err(dev->dev, "timeout wait pmu cmd\n");
0025         return err;
0026     }
0027
0028     pmu_write(LIMA_PMU_INT_CLEAR, LIMA_PMU_INT_CMD_MASK);
0029     return 0;
0030 }
0031
0032 static u32 lima_pmu_get_ip_mask(struct lima_ip *ip)
0033 {
0034     struct lima_device *dev = ip->dev;
0035     u32 ret = 0;
0036     int i;
0037
0038     ret |= LIMA_PMU_POWER_GP0_MASK;
0039
0040     if (dev->id == lima_gpu_mali400) {
0041         ret |= LIMA_PMU_POWER_L2_MASK;
0042         for (i = 0; i < 4; i++) {
0043             if (dev->ip[lima_ip_pp0 + i].present)
0044                 ret |= LIMA_PMU_POWER_PP_MASK(i);
0045         }
0046     } else {
0047         if (dev->ip[lima_ip_pp0].present)
0048             ret |= LIMA450_PMU_POWER_PP0_MASK;
0049         for (i = lima_ip_pp1; i <= lima_ip_pp3; i++) {
0050             if (dev->ip[i].present) {
0051                 ret |= LIMA450_PMU_POWER_PP13_MASK;
0052                 break;
0053             }
0054         }
0055         for (i = lima_ip_pp4; i <= lima_ip_pp7; i++) {
0056             if (dev->ip[i].present) {
0057                 ret |= LIMA450_PMU_POWER_PP47_MASK;
0058                 break;
0059             }
0060         }
0061     }
0062
0063     return ret;
0064 }
0065
0066 static int lima_pmu_hw_init(struct lima_ip *ip)
0067 {
0068     int err;
0069     u32 stat;
0070
0071     pmu_write(LIMA_PMU_INT_MASK, 0);
0072
0073     /* If this value is too low, when in high GPU clk freq,
0074      * GPU will be in unstable state.
0075      */
0076     pmu_write(LIMA_PMU_SW_DELAY, 0xffff);
0077
0078     /* status reg 1=off 0=on */
0079     stat = pmu_read(LIMA_PMU_STATUS);
0080
0081     /* power up all ip */
0082     if (stat) {
0083         pmu_write(LIMA_PMU_POWER_UP, stat);
0084         err = lima_pmu_wait_cmd(ip);
0085         if (err)
0086             return err;
0087     }
0088     return 0;
0089 }
0090
0091 static void lima_pmu_hw_fini(struct lima_ip *ip)
0092 {
0093     u32 stat;
0094
0095     if (!ip->data.mask)
0096         ip->data.mask = lima_pmu_get_ip_mask(ip);
0097
0098     stat = ~pmu_read(LIMA_PMU_STATUS) & ip->data.mask;
0099     if (stat) {
0100         pmu_write(LIMA_PMU_POWER_DOWN, stat);
0101
0102         /* Don't wait for interrupt on Mali400 if all domains are
0103          * powered off because the HW won't generate an interrupt
0104          * in this case.
0105          */
0106         if (ip->dev->id == lima_gpu_mali400)
0107             pmu_write(LIMA_PMU_INT_CLEAR, LIMA_PMU_INT_CMD_MASK);
0108         else
0109             lima_pmu_wait_cmd(ip);
0110     }
0111 }
0112
0113 int lima_pmu_resume(struct lima_ip *ip)
0114 {
0115     return lima_pmu_hw_init(ip);
0116 }
0117
0118 void lima_pmu_suspend(struct lima_ip *ip)
0119 {
0120     lima_pmu_hw_fini(ip);
0121 }
0122
0123 int lima_pmu_init(struct lima_ip *ip)
0124 {
0125     return lima_pmu_hw_init(ip);
0126 }
0127
0128 void lima_pmu_fini(struct lima_ip *ip)
0129 {
0130     lima_pmu_hw_fini(ip);
0131 }