drm/lima/lima_l2_cache.c

0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
0003
0004 #include <linux/iopoll.h>
0005 #include <linux/device.h>
0006
0007 #include "lima_device.h"
0008 #include "lima_l2_cache.h"
0009 #include "lima_regs.h"
0010
0011 #define l2_cache_write(reg, data) writel(data, ip->iomem + reg)
0012 #define l2_cache_read(reg) readl(ip->iomem + reg)
0013
0014 static int lima_l2_cache_wait_idle(struct lima_ip *ip)
0015 {
0016     struct lima_device *dev = ip->dev;
0017     int err;
0018     u32 v;
0019
0020     err = readl_poll_timeout(ip->iomem + LIMA_L2_CACHE_STATUS, v,
0021                  !(v & LIMA_L2_CACHE_STATUS_COMMAND_BUSY),
0022                  0, 1000);
0023     if (err) {
0024         dev_err(dev->dev, "l2 cache wait command timeout\n");
0025         return err;
0026     }
0027     return 0;
0028 }
0029
0030 int lima_l2_cache_flush(struct lima_ip *ip)
0031 {
0032     int ret;
0033
0034     spin_lock(&ip->data.lock);
0035     l2_cache_write(LIMA_L2_CACHE_COMMAND, LIMA_L2_CACHE_COMMAND_CLEAR_ALL);
0036     ret = lima_l2_cache_wait_idle(ip);
0037     spin_unlock(&ip->data.lock);
0038     return ret;
0039 }
0040
0041 static int lima_l2_cache_hw_init(struct lima_ip *ip)
0042 {
0043     int err;
0044
0045     err = lima_l2_cache_flush(ip);
0046     if (err)
0047         return err;
0048
0049     l2_cache_write(LIMA_L2_CACHE_ENABLE,
0050                LIMA_L2_CACHE_ENABLE_ACCESS |
0051                LIMA_L2_CACHE_ENABLE_READ_ALLOCATE);
0052     l2_cache_write(LIMA_L2_CACHE_MAX_READS, 0x1c);
0053
0054     return 0;
0055 }
0056
0057 int lima_l2_cache_resume(struct lima_ip *ip)
0058 {
0059     return lima_l2_cache_hw_init(ip);
0060 }
0061
0062 void lima_l2_cache_suspend(struct lima_ip *ip)
0063 {
0064
0065 }
0066
0067 int lima_l2_cache_init(struct lima_ip *ip)
0068 {
0069     int i;
0070     u32 size;
0071     struct lima_device *dev = ip->dev;
0072
0073     /* l2_cache2 only exists when one of PP4-7 present */
0074     if (ip->id == lima_ip_l2_cache2) {
0075         for (i = lima_ip_pp4; i <= lima_ip_pp7; i++) {
0076             if (dev->ip[i].present)
0077                 break;
0078         }
0079         if (i > lima_ip_pp7)
0080             return -ENODEV;
0081     }
0082
0083     spin_lock_init(&ip->data.lock);
0084
0085     size = l2_cache_read(LIMA_L2_CACHE_SIZE);
0086     dev_info(dev->dev, "l2 cache %uK, %u-way, %ubyte cache line, %ubit external bus\n",
0087          1 << (((size >> 16) & 0xff) - 10),
0088          1 << ((size >> 8) & 0xff),
0089          1 << (size & 0xff),
0090          1 << ((size >> 24) & 0xff));
0091
0092     return lima_l2_cache_hw_init(ip);
0093 }
0094
0095 void lima_l2_cache_fini(struct lima_ip *ip)
0096 {
0097
0098 }