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0006 #ifndef __KMB_REGS_H__
0007 #define __KMB_REGS_H__
0008
0009
0010
0011
0012 #define LCD_CONTROL (0x4 * 0x000)
0013 #define LCD_CTRL_PROGRESSIVE (0 << 0)
0014 #define LCD_CTRL_INTERLACED BIT(0)
0015 #define LCD_CTRL_ENABLE BIT(1)
0016 #define LCD_CTRL_VL1_ENABLE BIT(2)
0017 #define LCD_CTRL_VL2_ENABLE BIT(3)
0018 #define LCD_CTRL_GL1_ENABLE BIT(4)
0019 #define LCD_CTRL_GL2_ENABLE BIT(5)
0020 #define LCD_CTRL_ALPHA_BLEND_VL1 (0 << 6)
0021 #define LCD_CTRL_ALPHA_BLEND_VL2 BIT(6)
0022 #define LCD_CTRL_ALPHA_BLEND_GL1 (2 << 6)
0023 #define LCD_CTRL_ALPHA_BLEND_GL2 (3 << 6)
0024 #define LCD_CTRL_ALPHA_TOP_VL1 (0 << 8)
0025 #define LCD_CTRL_ALPHA_TOP_VL2 BIT(8)
0026 #define LCD_CTRL_ALPHA_TOP_GL1 (2 << 8)
0027 #define LCD_CTRL_ALPHA_TOP_GL2 (3 << 8)
0028 #define LCD_CTRL_ALPHA_MIDDLE_VL1 (0 << 10)
0029 #define LCD_CTRL_ALPHA_MIDDLE_VL2 BIT(10)
0030 #define LCD_CTRL_ALPHA_MIDDLE_GL1 (2 << 10)
0031 #define LCD_CTRL_ALPHA_MIDDLE_GL2 (3 << 10)
0032 #define LCD_CTRL_ALPHA_BOTTOM_VL1 (0 << 12)
0033 #define LCD_CTRL_ALPHA_BOTTOM_VL2 BIT(12)
0034 #define LCD_CTRL_ALPHA_BOTTOM_GL1 (2 << 12)
0035 #define LCD_CTRL_ALPHA_BOTTOM_GL2 (3 << 12)
0036 #define LCD_CTRL_TIM_GEN_ENABLE BIT(14)
0037 #define LCD_CTRL_CONTINUOUS (0 << 15)
0038 #define LCD_CTRL_ONE_SHOT BIT(15)
0039 #define LCD_CTRL_PWM0_EN BIT(16)
0040 #define LCD_CTRL_PWM1_EN BIT(17)
0041 #define LCD_CTRL_PWM2_EN BIT(18)
0042 #define LCD_CTRL_OUTPUT_DISABLED (0 << 19)
0043 #define LCD_CTRL_OUTPUT_ENABLED BIT(19)
0044 #define LCD_CTRL_BPORCH_ENABLE BIT(21)
0045 #define LCD_CTRL_FPORCH_ENABLE BIT(22)
0046 #define LCD_CTRL_ALPHA_BLEND_BKGND_DISABLE BIT(23)
0047 #define LCD_CTRL_PIPELINE_DMA BIT(28)
0048 #define LCD_CTRL_VHSYNC_IDLE_LVL BIT(31)
0049 #define LCD_CTRL_ALPHA_ALL (0xff << 6)
0050
0051
0052 #define LCD_INT_STATUS (0x4 * 0x001)
0053 #define LCD_INT_EOF BIT(0)
0054 #define LCD_INT_LINE_CMP BIT(1)
0055 #define LCD_INT_VERT_COMP BIT(2)
0056 #define LAYER0_DMA_DONE BIT(3)
0057 #define LAYER0_DMA_IDLE BIT(4)
0058 #define LAYER0_DMA_FIFO_OVERFLOW BIT(5)
0059 #define LAYER0_DMA_FIFO_UNDERFLOW BIT(6)
0060 #define LAYER0_DMA_CB_FIFO_OVERFLOW BIT(7)
0061 #define LAYER0_DMA_CB_FIFO_UNDERFLOW BIT(8)
0062 #define LAYER0_DMA_CR_FIFO_OVERFLOW BIT(9)
0063 #define LAYER0_DMA_CR_FIFO_UNDERFLOW BIT(10)
0064 #define LAYER1_DMA_DONE BIT(11)
0065 #define LAYER1_DMA_IDLE BIT(12)
0066 #define LAYER1_DMA_FIFO_OVERFLOW BIT(13)
0067 #define LAYER1_DMA_FIFO_UNDERFLOW BIT(14)
0068 #define LAYER1_DMA_CB_FIFO_OVERFLOW BIT(15)
0069 #define LAYER1_DMA_CB_FIFO_UNDERFLOW BIT(16)
0070 #define LAYER1_DMA_CR_FIFO_OVERFLOW BIT(17)
0071 #define LAYER1_DMA_CR_FIFO_UNDERFLOW BIT(18)
0072 #define LAYER2_DMA_DONE BIT(19)
0073 #define LAYER2_DMA_IDLE BIT(20)
0074 #define LAYER2_DMA_FIFO_OVERFLOW BIT(21)
0075 #define LAYER2_DMA_FIFO_UNDERFLOW BIT(22)
0076 #define LAYER3_DMA_DONE BIT(23)
0077 #define LAYER3_DMA_IDLE BIT(24)
0078 #define LAYER3_DMA_FIFO_OVERFLOW BIT(25)
0079 #define LAYER3_DMA_FIFO_UNDERFLOW BIT(26)
0080 #define LCD_INT_LAYER (0x07fffff8)
0081 #define LCD_INT_ENABLE (0x4 * 0x002)
0082 #define LCD_INT_CLEAR (0x4 * 0x003)
0083 #define LCD_LINE_COUNT (0x4 * 0x004)
0084 #define LCD_LINE_COMPARE (0x4 * 0x005)
0085 #define LCD_VSTATUS (0x4 * 0x006)
0086
0087
0088
0089
0090
0091 #define LCD_VSTATUS_COMPARE (0x4 * 0x007)
0092 #define LCD_VSTATUS_VERTICAL_STATUS_MASK (3 << 13)
0093 #define LCD_VSTATUS_COMPARE_VSYNC (0 << 13)
0094 #define LCD_VSTATUS_COMPARE_BACKPORCH BIT(13)
0095 #define LCD_VSTATUS_COMPARE_ACTIVE (2 << 13)
0096 #define LCD_VSTATUS_COMPARE_FRONT_PORCH (3 << 13)
0097
0098 #define LCD_SCREEN_WIDTH (0x4 * 0x008)
0099 #define LCD_SCREEN_HEIGHT (0x4 * 0x009)
0100 #define LCD_FIELD_INT_CFG (0x4 * 0x00a)
0101 #define LCD_FIFO_FLUSH (0x4 * 0x00b)
0102 #define LCD_BG_COLOUR_LS (0x4 * 0x00c)
0103 #define LCD_BG_COLOUR_MS (0x4 * 0x00d)
0104 #define LCD_RAM_CFG (0x4 * 0x00e)
0105
0106
0107
0108
0109 #define LCD_LAYER0_CFG (0x4 * 0x100)
0110 #define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400 * (N)))
0111 #define LCD_LAYER_SCALE_H BIT(1)
0112 #define LCD_LAYER_SCALE_V BIT(2)
0113 #define LCD_LAYER_SCALE_H_V (LCD_LAYER_SCALE_H | \
0114 LCD_LAYER_SCALE_V)
0115 #define LCD_LAYER_CSC_EN BIT(3)
0116 #define LCD_LAYER_ALPHA_STATIC BIT(4)
0117 #define LCD_LAYER_ALPHA_EMBED BIT(5)
0118 #define LCD_LAYER_ALPHA_COMBI (LCD_LAYER_ALPHA_STATIC | \
0119 LCD_LAYER_ALPHA_EMBED)
0120 #define LCD_LAYER_ALPHA_DISABLED ~(LCD_LAYER_ALPHA_COMBI)
0121
0122 #define LCD_LAYER_ALPHA_PREMULT BIT(6)
0123 #define LCD_LAYER_INVERT_COL BIT(7)
0124 #define LCD_LAYER_TRANSPARENT_EN BIT(8)
0125 #define LCD_LAYER_FORMAT_YCBCR444PLAN (0 << 9)
0126 #define LCD_LAYER_FORMAT_YCBCR422PLAN BIT(9)
0127 #define LCD_LAYER_FORMAT_YCBCR420PLAN (2 << 9)
0128 #define LCD_LAYER_FORMAT_RGB888PLAN (3 << 9)
0129 #define LCD_LAYER_FORMAT_YCBCR444LIN (4 << 9)
0130 #define LCD_LAYER_FORMAT_YCBCR422LIN (5 << 9)
0131 #define LCD_LAYER_FORMAT_RGB888 (6 << 9)
0132 #define LCD_LAYER_FORMAT_RGBA8888 (7 << 9)
0133 #define LCD_LAYER_FORMAT_RGBX8888 (8 << 9)
0134 #define LCD_LAYER_FORMAT_RGB565 (9 << 9)
0135 #define LCD_LAYER_FORMAT_RGBA1555 (0xa << 9)
0136 #define LCD_LAYER_FORMAT_XRGB1555 (0xb << 9)
0137 #define LCD_LAYER_FORMAT_RGB444 (0xc << 9)
0138 #define LCD_LAYER_FORMAT_RGBA4444 (0xd << 9)
0139 #define LCD_LAYER_FORMAT_RGBX4444 (0xe << 9)
0140 #define LCD_LAYER_FORMAT_RGB332 (0xf << 9)
0141 #define LCD_LAYER_FORMAT_RGBA3328 (0x10 << 9)
0142 #define LCD_LAYER_FORMAT_RGBX3328 (0x11 << 9)
0143 #define LCD_LAYER_FORMAT_CLUT (0x12 << 9)
0144 #define LCD_LAYER_FORMAT_NV12 (0x1c << 9)
0145 #define LCD_LAYER_PLANAR_STORAGE BIT(14)
0146 #define LCD_LAYER_8BPP (0 << 15)
0147 #define LCD_LAYER_16BPP BIT(15)
0148 #define LCD_LAYER_24BPP (2 << 15)
0149 #define LCD_LAYER_32BPP (3 << 15)
0150 #define LCD_LAYER_Y_ORDER BIT(17)
0151 #define LCD_LAYER_CRCB_ORDER BIT(18)
0152 #define LCD_LAYER_BGR_ORDER BIT(19)
0153 #define LCD_LAYER_LUT_2ENT (0 << 20)
0154 #define LCD_LAYER_LUT_4ENT BIT(20)
0155 #define LCD_LAYER_LUT_16ENT (2 << 20)
0156 #define LCD_LAYER_NO_FLIP (0 << 22)
0157 #define LCD_LAYER_FLIP_V BIT(22)
0158 #define LCD_LAYER_FLIP_H (2 << 22)
0159 #define LCD_LAYER_ROT_R90 (3 << 22)
0160 #define LCD_LAYER_ROT_L90 (4 << 22)
0161 #define LCD_LAYER_ROT_180 (5 << 22)
0162 #define LCD_LAYER_FIFO_00 (0 << 25)
0163 #define LCD_LAYER_FIFO_25 BIT(25)
0164 #define LCD_LAYER_FIFO_50 (2 << 25)
0165 #define LCD_LAYER_FIFO_100 (3 << 25)
0166 #define LCD_LAYER_INTERLEAVE_DIS (0 << 27)
0167 #define LCD_LAYER_INTERLEAVE_V BIT(27)
0168 #define LCD_LAYER_INTERLEAVE_H (2 << 27)
0169 #define LCD_LAYER_INTERLEAVE_CH (3 << 27)
0170 #define LCD_LAYER_INTERLEAVE_V_SUB (4 << 27)
0171 #define LCD_LAYER_INTERLEAVE_H_SUB (5 << 27)
0172 #define LCD_LAYER_INTERLEAVE_CH_SUB (6 << 27)
0173 #define LCD_LAYER_INTER_POS_EVEN (0 << 30)
0174 #define LCD_LAYER_INTER_POS_ODD BIT(30)
0175
0176 #define LCD_LAYER0_COL_START (0x4 * 0x101)
0177 #define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400 * (N)))
0178 #define LCD_LAYER0_ROW_START (0x4 * 0x102)
0179 #define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400 * (N)))
0180 #define LCD_LAYER0_WIDTH (0x4 * 0x103)
0181 #define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400 * (N)))
0182 #define LCD_LAYER0_HEIGHT (0x4 * 0x104)
0183 #define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400 * (N)))
0184 #define LCD_LAYER0_SCALE_CFG (0x4 * 0x105)
0185 #define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400 * (N)))
0186 #define LCD_LAYER0_ALPHA (0x4 * 0x106)
0187 #define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400 * (N)))
0188 #define LCD_LAYER0_INV_COLOUR_LS (0x4 * 0x107)
0189 #define LCD_LAYERn_INV_COLOUR_LS(N) (LCD_LAYER0_INV_COLOUR_LS + \
0190 (0x400 * (N)))
0191 #define LCD_LAYER0_INV_COLOUR_MS (0x4 * 0x108)
0192 #define LCD_LAYERn_INV_COLOUR_MS(N) (LCD_LAYER0_INV_COLOUR_MS + \
0193 (0x400 * (N)))
0194 #define LCD_LAYER0_TRANS_COLOUR_LS (0x4 * 0x109)
0195 #define LCD_LAYERn_TRANS_COLOUR_LS(N) (LCD_LAYER0_TRANS_COLOUR_LS + \
0196 (0x400 * (N)))
0197 #define LCD_LAYER0_TRANS_COLOUR_MS (0x4 * 0x10a)
0198 #define LCD_LAYERn_TRANS_COLOUR_MS(N) (LCD_LAYER0_TRANS_COLOUR_MS + \
0199 (0x400 * (N)))
0200 #define LCD_LAYER0_CSC_COEFF11 (0x4 * 0x10b)
0201 #define LCD_LAYERn_CSC_COEFF11(N) (LCD_LAYER0_CSC_COEFF11 + (0x400 * (N)))
0202 #define LCD_LAYER0_CSC_COEFF12 (0x4 * 0x10c)
0203 #define LCD_LAYERn_CSC_COEFF12(N) (LCD_LAYER0_CSC_COEFF12 + (0x400 * (N)))
0204 #define LCD_LAYER0_CSC_COEFF13 (0x4 * 0x10d)
0205 #define LCD_LAYERn_CSC_COEFF13(N) (LCD_LAYER0_CSC_COEFF13 + (0x400 * (N)))
0206 #define LCD_LAYER0_CSC_COEFF21 (0x4 * 0x10e)
0207 #define LCD_LAYERn_CSC_COEFF21(N) (LCD_LAYER0_CSC_COEFF21 + (0x400 * (N)))
0208 #define LCD_LAYER0_CSC_COEFF22 (0x4 * 0x10f)
0209 #define LCD_LAYERn_CSC_COEFF22(N) (LCD_LAYER0_CSC_COEFF22 + (0x400 * (N)))
0210 #define LCD_LAYER0_CSC_COEFF23 (0x4 * 0x110)
0211 #define LCD_LAYERn_CSC_COEFF23(N) (LCD_LAYER0_CSC_COEFF23 + (0x400 * (N)))
0212 #define LCD_LAYER0_CSC_COEFF31 (0x4 * 0x111)
0213 #define LCD_LAYERn_CSC_COEFF31(N) (LCD_LAYER0_CSC_COEFF31 + (0x400 * (N)))
0214 #define LCD_LAYER0_CSC_COEFF32 (0x4 * 0x112)
0215 #define LCD_LAYERn_CSC_COEFF32(N) (LCD_LAYER0_CSC_COEFF32 + (0x400 * (N)))
0216 #define LCD_LAYER0_CSC_COEFF33 (0x4 * 0x113)
0217 #define LCD_LAYERn_CSC_COEFF33(N) (LCD_LAYER0_CSC_COEFF33 + (0x400 * (N)))
0218 #define LCD_LAYER0_CSC_OFF1 (0x4 * 0x114)
0219 #define LCD_LAYERn_CSC_OFF1(N) (LCD_LAYER0_CSC_OFF1 + (0x400 * (N)))
0220 #define LCD_LAYER0_CSC_OFF2 (0x4 * 0x115)
0221 #define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400 * (N)))
0222 #define LCD_LAYER0_CSC_OFF3 (0x4 * 0x116)
0223 #define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400 * (N)))
0224
0225
0226 #define LCD_LAYER0_DMA_CFG (0x4 * 0x117)
0227 #define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + \
0228 (0x400 * (N)))
0229 #define LCD_DMA_LAYER_ENABLE BIT(0)
0230 #define LCD_DMA_LAYER_STATUS BIT(1)
0231 #define LCD_DMA_LAYER_AUTO_UPDATE BIT(2)
0232 #define LCD_DMA_LAYER_CONT_UPDATE BIT(3)
0233 #define LCD_DMA_LAYER_CONT_PING_PONG_UPDATE (LCD_DMA_LAYER_AUTO_UPDATE \
0234 | LCD_DMA_LAYER_CONT_UPDATE)
0235 #define LCD_DMA_LAYER_FIFO_ADR_MODE BIT(4)
0236 #define LCD_DMA_LAYER_AXI_BURST_1 BIT(5)
0237 #define LCD_DMA_LAYER_AXI_BURST_2 (2 << 5)
0238 #define LCD_DMA_LAYER_AXI_BURST_3 (3 << 5)
0239 #define LCD_DMA_LAYER_AXI_BURST_4 (4 << 5)
0240 #define LCD_DMA_LAYER_AXI_BURST_5 (5 << 5)
0241 #define LCD_DMA_LAYER_AXI_BURST_6 (6 << 5)
0242 #define LCD_DMA_LAYER_AXI_BURST_7 (7 << 5)
0243 #define LCD_DMA_LAYER_AXI_BURST_8 (8 << 5)
0244 #define LCD_DMA_LAYER_AXI_BURST_9 (9 << 5)
0245 #define LCD_DMA_LAYER_AXI_BURST_10 (0xa << 5)
0246 #define LCD_DMA_LAYER_AXI_BURST_11 (0xb << 5)
0247 #define LCD_DMA_LAYER_AXI_BURST_12 (0xc << 5)
0248 #define LCD_DMA_LAYER_AXI_BURST_13 (0xd << 5)
0249 #define LCD_DMA_LAYER_AXI_BURST_14 (0xe << 5)
0250 #define LCD_DMA_LAYER_AXI_BURST_15 (0xf << 5)
0251 #define LCD_DMA_LAYER_AXI_BURST_16 (0x10 << 5)
0252 #define LCD_DMA_LAYER_VSTRIDE_EN BIT(10)
0253
0254 #define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118)
0255 #define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR \
0256 + (0x400 * (N)))
0257 #define LCD_LAYER0_DMA_START_SHADOW (0x4 * 0x119)
0258 #define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW \
0259 + (0x400 * (N)))
0260 #define LCD_LAYER0_DMA_LEN (0x4 * 0x11a)
0261 #define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + \
0262 (0x400 * (N)))
0263 #define LCD_LAYER0_DMA_LEN_SHADOW (0x4 * 0x11b)
0264 #define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + \
0265 (0x400 * (N)))
0266 #define LCD_LAYER0_DMA_STATUS (0x4 * 0x11c)
0267 #define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + \
0268 (0x400 * (N)))
0269 #define LCD_LAYER0_DMA_LINE_WIDTH (0x4 * 0x11d)
0270 #define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + \
0271 (0x400 * (N)))
0272 #define LCD_LAYER0_DMA_LINE_VSTRIDE (0x4 * 0x11e)
0273 #define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE +\
0274 (0x400 * (N)))
0275 #define LCD_LAYER0_DMA_FIFO_STATUS (0x4 * 0x11f)
0276 #define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + \
0277 (0x400 * (N)))
0278 #define LCD_LAYER0_CFG2 (0x4 * 0x120)
0279 #define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400 * (N)))
0280 #define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700)
0281 #define LCD_LAYERn_DMA_START_CB_ADR(N) (LCD_LAYER0_DMA_START_CB_ADR + \
0282 (0x20 * (N)))
0283 #define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701)
0284 #define LCD_LAYERn_DMA_START_CB_SHADOW(N) (LCD_LAYER0_DMA_START_CB_SHADOW\
0285 + (0x20 * (N)))
0286 #define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702)
0287 #define LCD_LAYERn_DMA_CB_LINE_WIDTH(N) (LCD_LAYER0_DMA_CB_LINE_WIDTH +\
0288 (0x20 * (N)))
0289 #define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703)
0290 #define LCD_LAYERn_DMA_CB_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_CB_LINE_VSTRIDE\
0291 + (0x20 * (N)))
0292 #define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704)
0293 #define LCD_LAYERn_DMA_START_CR_ADR(N) (LCD_LAYER0_DMA_START_CR_ADR + \
0294 (0x20 * (N)))
0295 #define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705)
0296 #define LCD_LAYERn_DMA_START_CR_SHADOW(N) \
0297 (LCD_LAYER0_DMA_START_CR_SHADOW\
0298 + (0x20 * (N)))
0299 #define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706)
0300 #define LCD_LAYERn_DMA_CR_LINE_WIDTH(N) (LCD_LAYER0_DMA_CR_LINE_WIDTH +\
0301 (0x20 * (N)))
0302 #define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707)
0303 #define LCD_LAYERn_DMA_CR_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_CR_LINE_VSTRIDE\
0304 + (0x20 * (N)))
0305 #define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708)
0306 #define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709)
0307 #define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a)
0308 #define LCD_LAYER1_DMA_CB_LINE_VSTRIDE (0x4 * 0x70b)
0309 #define LCD_LAYER1_DMA_START_CR_ADR (0x4 * 0x70c)
0310 #define LCD_LAYER1_DMA_START_CR_SHADOW (0x4 * 0x70d)
0311 #define LCD_LAYER1_DMA_CR_LINE_WIDTH (0x4 * 0x70e)
0312 #define LCD_LAYER1_DMA_CR_LINE_VSTRIDE (0x4 * 0x70f)
0313
0314
0315
0316
0317 #define LCD_OUT_FORMAT_CFG (0x4 * 0x800)
0318 #define LCD_OUTF_FORMAT_RGB121212 (0x00)
0319 #define LCD_OUTF_FORMAT_RGB101010 (0x01)
0320 #define LCD_OUTF_FORMAT_RGB888 (0x02)
0321 #define LCD_OUTF_FORMAT_RGB666 (0x03)
0322 #define LCD_OUTF_FORMAT_RGB565 (0x04)
0323 #define LCD_OUTF_FORMAT_RGB444 (0x05)
0324 #define LCD_OUTF_FORMAT_MRGB121212 (0x10)
0325 #define LCD_OUTF_FORMAT_MRGB101010 (0x11)
0326 #define LCD_OUTF_FORMAT_MRGB888 (0x12)
0327 #define LCD_OUTF_FORMAT_MRGB666 (0x13)
0328 #define LCD_OUTF_FORMAT_MRGB565 (0x14)
0329 #define LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08)
0330 #define LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09)
0331 #define LCD_OUTF_FORMAT_YCBCR420_8B (0x0A)
0332 #define LCD_OUTF_FORMAT_YCBCR420_10B (0x0B)
0333 #define LCD_OUTF_FORMAT_YCBCR420_12B (0x0C)
0334 #define LCD_OUTF_FORMAT_YCBCR422_8B (0x0D)
0335 #define LCD_OUTF_FORMAT_YCBCR422_10B (0x0E)
0336 #define LCD_OUTF_FORMAT_YCBCR444 (0x0F)
0337 #define LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18)
0338 #define LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19)
0339 #define LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A)
0340 #define LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B)
0341 #define LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C)
0342 #define LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D)
0343 #define LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E)
0344 #define LCD_OUTF_FORMAT_MYCBCR444 (0x1F)
0345 #define LCD_OUTF_BGR_ORDER BIT(5)
0346 #define LCD_OUTF_Y_ORDER BIT(6)
0347 #define LCD_OUTF_CRCB_ORDER BIT(7)
0348 #define LCD_OUTF_SYNC_MODE BIT(11)
0349 #define LCD_OUTF_RGB_CONV_MODE BIT(14)
0350 #define LCD_OUTF_MIPI_RGB_MODE BIT(18)
0351
0352 #define LCD_HSYNC_WIDTH (0x4 * 0x801)
0353 #define LCD_H_BACKPORCH (0x4 * 0x802)
0354 #define LCD_H_ACTIVEWIDTH (0x4 * 0x803)
0355 #define LCD_H_FRONTPORCH (0x4 * 0x804)
0356 #define LCD_VSYNC_WIDTH (0x4 * 0x805)
0357 #define LCD_V_BACKPORCH (0x4 * 0x806)
0358 #define LCD_V_ACTIVEHEIGHT (0x4 * 0x807)
0359 #define LCD_V_FRONTPORCH (0x4 * 0x808)
0360 #define LCD_VSYNC_START (0x4 * 0x809)
0361 #define LCD_VSYNC_END (0x4 * 0x80a)
0362 #define LCD_V_BACKPORCH_EVEN (0x4 * 0x80b)
0363 #define LCD_VSYNC_WIDTH_EVEN (0x4 * 0x80c)
0364 #define LCD_V_ACTIVEHEIGHT_EVEN (0x4 * 0x80d)
0365 #define LCD_V_FRONTPORCH_EVEN (0x4 * 0x80e)
0366 #define LCD_VSYNC_START_EVEN (0x4 * 0x80f)
0367 #define LCD_VSYNC_END_EVEN (0x4 * 0x810)
0368 #define LCD_TIMING_GEN_TRIG (0x4 * 0x811)
0369 #define LCD_PWM0_CTRL (0x4 * 0x812)
0370 #define LCD_PWM0_RPT_LEADIN (0x4 * 0x813)
0371 #define LCD_PWM0_HIGH_LOW (0x4 * 0x814)
0372 #define LCD_PWM1_CTRL (0x4 * 0x815)
0373 #define LCD_PWM1_RPT_LEADIN (0x4 * 0x816)
0374 #define LCD_PWM1_HIGH_LOW (0x4 * 0x817)
0375 #define LCD_PWM2_CTRL (0x4 * 0x818)
0376 #define LCD_PWM2_RPT_LEADIN (0x4 * 0x819)
0377 #define LCD_PWM2_HIGH_LOW (0x4 * 0x81a)
0378 #define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00)
0379 #define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01)
0380 #define LCD_DMA_STATE_ACTIVE BIT(3)
0381 #define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02)
0382 #define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03)
0383 #define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04)
0384 #define LCD_VIDEO0_DMA2_STATE (0x4 * 0xb05)
0385 #define LCD_VIDEO1_DMA0_BYTES (0x4 * 0xb06)
0386 #define LCD_VIDEO1_DMA0_STATE (0x4 * 0xb07)
0387 #define LCD_VIDEO1_DMA1_BYTES (0x4 * 0xb08)
0388 #define LCD_VIDEO1_DMA1_STATE (0x4 * 0xb09)
0389 #define LCD_VIDEO1_DMA2_BYTES (0x4 * 0xb0a)
0390 #define LCD_VIDEO1_DMA2_STATE (0x4 * 0xb0b)
0391 #define LCD_GRAPHIC0_DMA_BYTES (0x4 * 0xb0c)
0392 #define LCD_GRAPHIC0_DMA_STATE (0x4 * 0xb0d)
0393 #define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e)
0394 #define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f)
0395
0396
0397
0398
0399 #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400)
0400 #define HS_OFFSET(M) (((M) + 1) * 0x400)
0401
0402 #define MIPI_TX_HS_CTRL (0x0)
0403 #define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M))
0404 #define HS_CTRL_EN BIT(0)
0405
0406 #define HS_CTRL_CSIDSIN BIT(2)
0407
0408 #define TX_SOURCE BIT(3)
0409 #define ACTIVE_LANES(n) ((n) << 4)
0410 #define LCD_VC(ch) ((ch) << 8)
0411 #define DSI_EOTP_EN BIT(11)
0412 #define DSI_CMD_HFP_EN BIT(12)
0413 #define CRC_EN BIT(14)
0414 #define HSEXIT_CNT(n) ((n) << 16)
0415 #define HSCLKIDLE_CNT BIT(24)
0416 #define MIPI_TX_HS_SYNC_CFG (0x8)
0417 #define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \
0418 + HS_OFFSET(M))
0419 #define LINE_SYNC_PKT_ENABLE BIT(0)
0420 #define FRAME_COUNTER_ACTIVE BIT(1)
0421 #define LINE_COUNTER_ACTIVE BIT(2)
0422 #define DSI_V_BLANKING BIT(4)
0423 #define DSI_HSA_BLANKING BIT(5)
0424 #define DSI_HBP_BLANKING BIT(6)
0425 #define DSI_HFP_BLANKING BIT(7)
0426 #define DSI_SYNC_PULSE_EVENTN BIT(8)
0427 #define DSI_LPM_FIRST_VSA_LINE BIT(9)
0428 #define DSI_LPM_LAST_VFP_LINE BIT(10)
0429 #define WAIT_ALL_SECT BIT(11)
0430 #define WAIT_TRIG_POS BIT(15)
0431 #define ALWAYS_USE_HACT(f) ((f) << 19)
0432 #define FRAME_GEN_EN(f) ((f) << 23)
0433 #define HACT_WAIT_STOP(f) ((f) << 28)
0434 #define MIPI_TX0_HS_FG0_SECT0_PH (0x40)
0435 #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \
0436 HS_OFFSET(M) + (0x2C * (N)) \
0437 + (8 * (O)))
0438 #define MIPI_TX_SECT_WC_MASK (0xffff)
0439 #define MIPI_TX_SECT_VC_MASK (3)
0440 #define MIPI_TX_SECT_VC_SHIFT (22)
0441 #define MIPI_TX_SECT_DT_MASK (0x3f)
0442 #define MIPI_TX_SECT_DT_SHIFT (16)
0443 #define MIPI_TX_SECT_DM_MASK (3)
0444 #define MIPI_TX_SECT_DM_SHIFT (24)
0445 #define MIPI_TX_SECT_DMA_PACKED BIT(26)
0446 #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60)
0447 #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64)
0448 #define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \
0449 (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 \
0450 + HS_OFFSET(M) + (0x2C * (N)))
0451 #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44)
0452 #define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \
0453 (MIPI_TX_HS_FG0_SECT0_LINE_CFG + HS_OFFSET(M) \
0454 + (0x2C * (N)) + (8 * (O)))
0455
0456 #define MIPI_TX_HS_FG0_NUM_LINES (0x68)
0457 #define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \
0458 (MIPI_TX_HS_FG0_NUM_LINES + HS_OFFSET(M) \
0459 + (0x2C * (N)))
0460 #define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104)
0461 #define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \
0462 (MIPI_TX_HS_VSYNC_WIDTHS0 + HS_OFFSET(M) \
0463 + (0x4 * (N)))
0464 #define MIPI_TX_HS_V_BACKPORCHES0 (0x16c)
0465 #define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \
0466 (MIPI_TX_HS_V_BACKPORCHES0 + HS_OFFSET(M) \
0467 + (0x4 * (N)))
0468 #define MIPI_TX_HS_V_FRONTPORCHES0 (0x174)
0469 #define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \
0470 (MIPI_TX_HS_V_FRONTPORCHES0 + HS_OFFSET(M) \
0471 + (0x4 * (N)))
0472 #define MIPI_TX_HS_V_ACTIVE0 (0x17c)
0473 #define MIPI_TXm_HS_V_ACTIVEn(M, N) \
0474 (MIPI_TX_HS_V_ACTIVE0 + HS_OFFSET(M) \
0475 + (0x4 * (N)))
0476 #define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c)
0477 #define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) \
0478 (MIPI_TX_HS_HSYNC_WIDTH0 + HS_OFFSET(M) \
0479 + (0x4 * (N)))
0480 #define MIPI_TX_HS_H_BACKPORCH0 (0x11c)
0481 #define MIPI_TXm_HS_H_BACKPORCHn(M, N) \
0482 (MIPI_TX_HS_H_BACKPORCH0 + HS_OFFSET(M) \
0483 + (0x4 * (N)))
0484 #define MIPI_TX_HS_H_FRONTPORCH0 (0x12c)
0485 #define MIPI_TXm_HS_H_FRONTPORCHn(M, N) \
0486 (MIPI_TX_HS_H_FRONTPORCH0 + HS_OFFSET(M) \
0487 + (0x4 * (N)))
0488 #define MIPI_TX_HS_H_ACTIVE0 (0x184)
0489 #define MIPI_TXm_HS_H_ACTIVEn(M, N) \
0490 (MIPI_TX_HS_H_ACTIVE0 + HS_OFFSET(M) \
0491 + (0x4 * (N)))
0492 #define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c)
0493 #define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) \
0494 (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + HS_OFFSET(M) \
0495 + (0x4 * (N)))
0496 #define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c)
0497 #define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) \
0498 (MIPI_TX_HS_LLP_H_BACKPORCH0 + HS_OFFSET(M) \
0499 + (0x4 * (N)))
0500 #define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c)
0501 #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) \
0502 (MIPI_TX_HS_LLP_H_FRONTPORCH0 + HS_OFFSET(M) \
0503 + (0x4 * (N)))
0504
0505 #define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194)
0506 #define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) \
0507 (MIPI_TX_HS_MC_FIFO_CTRL_EN + HS_OFFSET(M))
0508
0509 #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198)
0510 #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c)
0511 #define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \
0512 (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \
0513 + (0x4 * (N)))
0514 #define SET_MC_FIFO_CHAN_ALLOC(dev, ctrl, vc, sz) \
0515 kmb_write_bits_mipi(dev, \
0516 MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, \
0517 (vc) / 2), ((vc) % 2) * 16, 16, sz)
0518 #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0)
0519 #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4)
0520 #define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \
0521 (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \
0522 + (0x4 * (N)))
0523 #define SET_MC_FIFO_RTHRESHOLD(dev, ctrl, vc, th) \
0524 kmb_write_bits_mipi(dev, MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, \
0525 (vc) / 2), ((vc) % 2) * 16, 16, th)
0526 #define MIPI_TX_HS_DMA_CFG (0x1a8)
0527 #define MIPI_TX_HS_DMA_START_ADR_CHAN0 (0x1ac)
0528 #define MIPI_TX_HS_DMA_LEN_CHAN0 (0x1b4)
0529
0530
0531 #define MIPI_CTRL_IRQ_STATUS0 (0x00)
0532 #define MIPI_DPHY_ERR_IRQ 1
0533 #define MIPI_DPHY_ERR_MASK 0x7FE
0534 #define MIPI_HS_IRQ 13
0535
0536 #define MIPI_HS_IRQ_MASK 0x7FE000
0537 #define MIPI_LP_EVENT_IRQ 25
0538 #define MIPI_GET_IRQ_STAT0(dev) kmb_read_mipi(dev, \
0539 MIPI_CTRL_IRQ_STATUS0)
0540 #define MIPI_CTRL_IRQ_STATUS1 (0x04)
0541 #define MIPI_HS_RX_EVENT_IRQ 0
0542 #define MIPI_GET_IRQ_STAT1(dev) kmb_read_mipi(dev, \
0543 MIPI_CTRL_IRQ_STATUS1)
0544 #define MIPI_CTRL_IRQ_ENABLE0 (0x08)
0545 #define SET_MIPI_CTRL_IRQ_ENABLE0(dev, M, N) kmb_set_bit_mipi(dev, \
0546 MIPI_CTRL_IRQ_ENABLE0, \
0547 (M) + (N))
0548 #define MIPI_GET_IRQ_ENABLED0(dev) kmb_read_mipi(dev, \
0549 MIPI_CTRL_IRQ_ENABLE0)
0550 #define MIPI_CTRL_IRQ_ENABLE1 (0x0c)
0551 #define MIPI_GET_IRQ_ENABLED1(dev) kmb_read_mipi(dev, \
0552 MIPI_CTRL_IRQ_ENABLE1)
0553 #define MIPI_CTRL_IRQ_CLEAR0 (0x010)
0554 #define SET_MIPI_CTRL_IRQ_CLEAR0(dev, M, N) \
0555 kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR0, (M) + (N))
0556 #define MIPI_CTRL_IRQ_CLEAR1 (0x014)
0557 #define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) \
0558 kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR1, (M) + (N))
0559 #define MIPI_CTRL_DIG_LOOPBACK (0x018)
0560 #define MIPI_TX_HS_IRQ_STATUS (0x01c)
0561 #define MIPI_TX_HS_IRQ_STATUSm(M) (MIPI_TX_HS_IRQ_STATUS + \
0562 HS_OFFSET(M))
0563 #define GET_MIPI_TX_HS_IRQ_STATUS(dev, M) kmb_read_mipi(dev, \
0564 MIPI_TX_HS_IRQ_STATUSm(M))
0565 #define MIPI_TX_HS_IRQ_LINE_COMPARE BIT(1)
0566 #define MIPI_TX_HS_IRQ_FRAME_DONE_0 BIT(2)
0567 #define MIPI_TX_HS_IRQ_FRAME_DONE_1 BIT(3)
0568 #define MIPI_TX_HS_IRQ_FRAME_DONE_2 BIT(4)
0569 #define MIPI_TX_HS_IRQ_FRAME_DONE_3 BIT(5)
0570 #define MIPI_TX_HS_IRQ_DMA_DONE_0 BIT(6)
0571 #define MIPI_TX_HS_IRQ_DMA_IDLE_0 BIT(7)
0572 #define MIPI_TX_HS_IRQ_DMA_DONE_1 BIT(8)
0573 #define MIPI_TX_HS_IRQ_DMA_IDLE_1 BIT(9)
0574 #define MIPI_TX_HS_IRQ_DMA_DONE_2 BIT(10)
0575 #define MIPI_TX_HS_IRQ_DMA_IDLE_2 BIT(11)
0576 #define MIPI_TX_HS_IRQ_DMA_DONE_3 BIT(12)
0577 #define MIPI_TX_HS_IRQ_DMA_IDLE_3 BIT(13)
0578 #define MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW BIT(14)
0579 #define MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW BIT(15)
0580 #define MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY BIT(16)
0581 #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL BIT(17)
0582 #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR BIT(18)
0583 #define MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR BIT(20)
0584 #define MIPI_TX_HS_IRQ_FRAME_DONE \
0585 (MIPI_TX_HS_IRQ_FRAME_DONE_0 | \
0586 MIPI_TX_HS_IRQ_FRAME_DONE_1 | \
0587 MIPI_TX_HS_IRQ_FRAME_DONE_2 | \
0588 MIPI_TX_HS_IRQ_FRAME_DONE_3)
0589
0590 #define MIPI_TX_HS_IRQ_DMA_DONE \
0591 (MIPI_TX_HS_IRQ_DMA_DONE_0 | \
0592 MIPI_TX_HS_IRQ_DMA_DONE_1 | \
0593 MIPI_TX_HS_IRQ_DMA_DONE_2 | \
0594 MIPI_TX_HS_IRQ_DMA_DONE_3)
0595
0596 #define MIPI_TX_HS_IRQ_DMA_IDLE \
0597 (MIPI_TX_HS_IRQ_DMA_IDLE_0 | \
0598 MIPI_TX_HS_IRQ_DMA_IDLE_1 | \
0599 MIPI_TX_HS_IRQ_DMA_IDLE_2 | \
0600 MIPI_TX_HS_IRQ_DMA_IDLE_3)
0601
0602 #define MIPI_TX_HS_IRQ_ERROR \
0603 (MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW | \
0604 MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW | \
0605 MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY | \
0606 MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL | \
0607 MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR | \
0608 MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR)
0609
0610 #define MIPI_TX_HS_IRQ_ALL \
0611 (MIPI_TX_HS_IRQ_FRAME_DONE | \
0612 MIPI_TX_HS_IRQ_DMA_DONE | \
0613 MIPI_TX_HS_IRQ_DMA_IDLE | \
0614 MIPI_TX_HS_IRQ_LINE_COMPARE | \
0615 MIPI_TX_HS_IRQ_ERROR)
0616
0617 #define MIPI_TX_HS_IRQ_ENABLE (0x020)
0618 #define GET_HS_IRQ_ENABLE(dev, M) kmb_read_mipi(dev, \
0619 MIPI_TX_HS_IRQ_ENABLE \
0620 + HS_OFFSET(M))
0621 #define MIPI_TX_HS_IRQ_CLEAR (0x024)
0622
0623
0624 #define MIPI_TX_HS_TEST_PAT_CTRL (0x230)
0625 #define MIPI_TXm_HS_TEST_PAT_CTRL(M) \
0626 (MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M))
0627 #define TP_EN_VCm(M) (1 << ((M) * 0x04))
0628 #define TP_SEL_VCm(M, N) \
0629 ((N) << (((M) * 0x04) + 1))
0630 #define TP_STRIPE_WIDTH(M) ((M) << 16)
0631 #define MIPI_TX_HS_TEST_PAT_COLOR0 (0x234)
0632 #define MIPI_TXm_HS_TEST_PAT_COLOR0(M) \
0633 (MIPI_TX_HS_TEST_PAT_COLOR0 + HS_OFFSET(M))
0634 #define MIPI_TX_HS_TEST_PAT_COLOR1 (0x238)
0635 #define MIPI_TXm_HS_TEST_PAT_COLOR1(M) \
0636 (MIPI_TX_HS_TEST_PAT_COLOR1 + HS_OFFSET(M))
0637
0638
0639 #define DPHY_ENABLE (0x100)
0640 #define DPHY_INIT_CTRL0 (0x104)
0641 #define SHUTDOWNZ 0
0642 #define RESETZ 12
0643 #define DPHY_INIT_CTRL1 (0x108)
0644 #define PLL_CLKSEL_0 18
0645 #define PLL_SHADOW_CTRL 16
0646 #define DPHY_INIT_CTRL2 (0x10c)
0647 #define SET_DPHY_INIT_CTRL0(dev, dphy, offset) \
0648 kmb_set_bit_mipi(dev, DPHY_INIT_CTRL0, \
0649 ((dphy) + (offset)))
0650 #define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) \
0651 kmb_clr_bit_mipi(dev, DPHY_INIT_CTRL0, \
0652 ((dphy) + (offset)))
0653 #define DPHY_INIT_CTRL2 (0x10c)
0654 #define DPHY_PLL_OBS0 (0x110)
0655 #define DPHY_PLL_OBS1 (0x114)
0656 #define DPHY_PLL_OBS2 (0x118)
0657 #define DPHY_FREQ_CTRL0_3 (0x11c)
0658 #define DPHY_FREQ_CTRL4_7 (0x120)
0659 #define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) \
0660 kmb_write_bits_mipi(dev, DPHY_FREQ_CTRL0_3 \
0661 + (((dphy) / 4) * 4), (dphy % 4) * 8, 6, val)
0662
0663 #define DPHY_FORCE_CTRL0 (0x128)
0664 #define DPHY_FORCE_CTRL1 (0x12C)
0665 #define MIPI_DPHY_STAT0_3 (0x134)
0666 #define MIPI_DPHY_STAT4_7 (0x138)
0667 #define GET_STOPSTATE_DATA(dev, dphy) \
0668 (((kmb_read_mipi(dev, MIPI_DPHY_STAT0_3 + \
0669 ((dphy) / 4) * 4)) >> \
0670 (((dphy % 4) * 8) + 4)) & 0x03)
0671
0672 #define MIPI_DPHY_ERR_STAT6_7 (0x14C)
0673
0674 #define DPHY_TEST_CTRL0 (0x154)
0675 #define SET_DPHY_TEST_CTRL0(dev, dphy) \
0676 kmb_set_bit_mipi(dev, DPHY_TEST_CTRL0, (dphy))
0677 #define CLR_DPHY_TEST_CTRL0(dev, dphy) \
0678 kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL0, \
0679 (dphy))
0680 #define DPHY_TEST_CTRL1 (0x158)
0681 #define SET_DPHY_TEST_CTRL1_CLK(dev, dphy) \
0682 kmb_set_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy))
0683 #define CLR_DPHY_TEST_CTRL1_CLK(dev, dphy) \
0684 kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy))
0685 #define SET_DPHY_TEST_CTRL1_EN(dev, dphy) \
0686 kmb_set_bit_mipi(dev, DPHY_TEST_CTRL1, ((dphy) + 12))
0687 #define CLR_DPHY_TEST_CTRL1_EN(dev, dphy) \
0688 kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL1, ((dphy) + 12))
0689 #define DPHY_TEST_DIN0_3 (0x15c)
0690 #define SET_TEST_DIN0_3(dev, dphy, val) \
0691 kmb_write_mipi(dev, DPHY_TEST_DIN0_3 + \
0692 4, ((val) << (((dphy) % 4) * 8)))
0693 #define DPHY_TEST_DOUT0_3 (0x168)
0694 #define GET_TEST_DOUT0_3(dev, dphy) \
0695 (kmb_read_mipi(dev, DPHY_TEST_DOUT0_3) \
0696 >> (((dphy) % 4) * 8) & 0xff)
0697 #define DPHY_TEST_DOUT4_7 (0x16C)
0698 #define GET_TEST_DOUT4_7(dev, dphy) \
0699 (kmb_read_mipi(dev, DPHY_TEST_DOUT4_7) \
0700 >> (((dphy) % 4) * 8) & 0xff)
0701 #define DPHY_TEST_DOUT8_9 (0x170)
0702 #define DPHY_TEST_DIN4_7 (0x160)
0703 #define DPHY_TEST_DIN8_9 (0x164)
0704 #define DPHY_PLL_LOCK (0x188)
0705 #define GET_PLL_LOCK(dev, dphy) \
0706 (kmb_read_mipi(dev, DPHY_PLL_LOCK) \
0707 & (1 << ((dphy) - MIPI_DPHY6)))
0708 #define DPHY_CFG_CLK_EN (0x18c)
0709
0710 #define MSS_MIPI_CIF_CFG (0x00)
0711 #define MSS_LCD_MIPI_CFG (0x04)
0712 #define MSS_CAM_CLK_CTRL (0x10)
0713 #define MSS_LOOPBACK_CFG (0x0C)
0714 #define LCD BIT(1)
0715 #define MIPI_COMMON BIT(2)
0716 #define MIPI_TX0 BIT(9)
0717 #define MSS_CAM_RSTN_CTRL (0x14)
0718 #define MSS_CAM_RSTN_SET (0x20)
0719 #define MSS_CAM_RSTN_CLR (0x24)
0720
0721 #define MSSCPU_CPR_CLK_EN (0x0)
0722 #define MSSCPU_CPR_RST_EN (0x10)
0723 #define BIT_MASK_16 (0xffff)
0724
0725 #define LCD_QOS_PRIORITY (0x8)
0726 #define LCD_QOS_MODE (0xC)
0727 #define LCD_QOS_BW (0x10)
0728 #endif
