drm/kmb/kmb_dsi.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  *
0003  * Copyright © 2019-2020 Intel Corporation
0004  */
0005
0006 #ifndef __KMB_DSI_H__
0007 #define __KMB_DSI_H__
0008
0009 #include <drm/drm_encoder.h>
0010 #include <drm/drm_mipi_dsi.h>
0011
0012 /* MIPI TX CFG */
0013 #define MIPI_TX_LANE_DATA_RATE_MBPS 891
0014 #define MIPI_TX_REF_CLK_KHZ         24000
0015 #define MIPI_TX_CFG_CLK_KHZ         24000
0016 #define MIPI_TX_BPP         24
0017
0018 /* DPHY Tx test codes*/
0019 #define TEST_CODE_FSM_CONTROL               0x03
0020 #define TEST_CODE_MULTIPLE_PHY_CTRL         0x0C
0021 #define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E
0022 #define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL     0x0F
0023 #define TEST_CODE_PLL_VCO_CTRL              0x12
0024 #define TEST_CODE_PLL_GMP_CTRL              0x13
0025 #define TEST_CODE_PLL_PHASE_ERR_CTRL            0x14
0026 #define TEST_CODE_PLL_LOCK_FILTER           0x15
0027 #define TEST_CODE_PLL_UNLOCK_FILTER         0x16
0028 #define TEST_CODE_PLL_INPUT_DIVIDER         0x17
0029 #define TEST_CODE_PLL_FEEDBACK_DIVIDER          0x18
0030 #define   PLL_FEEDBACK_DIVIDER_HIGH         BIT(7)
0031 #define TEST_CODE_PLL_OUTPUT_CLK_SEL            0x19
0032 #define   PLL_N_OVR_EN                  BIT(4)
0033 #define   PLL_M_OVR_EN                  BIT(5)
0034 #define TEST_CODE_VOD_LEVEL             0x24
0035 #define TEST_CODE_PLL_CHARGE_PUMP_BIAS          0x1C
0036 #define TEST_CODE_PLL_LOCK_DETECTOR         0x1D
0037 #define TEST_CODE_HS_FREQ_RANGE_CFG         0x44
0038 #define TEST_CODE_PLL_ANALOG_PROG           0x1F
0039 #define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL       0xA0
0040 #define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL       0xA3
0041 #define TEST_CODE_SLEW_RATE_DDL_CYCLES          0xA4
0042
0043 /* DPHY params */
0044 #define PLL_N_MIN   0
0045 #define PLL_N_MAX   15
0046 #define PLL_M_MIN   62
0047 #define PLL_M_MAX   623
0048 #define PLL_FVCO_MAX    1250
0049
0050 #define TIMEOUT     600
0051
0052 #define MIPI_TX_FRAME_GEN               4
0053 #define MIPI_TX_FRAME_GEN_SECTIONS          4
0054 #define MIPI_CTRL_VIRTUAL_CHANNELS          4
0055 #define MIPI_D_LANES_PER_DPHY               2
0056 #define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC         255
0057 #define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC         511
0058 /* 2 Data Lanes per D-PHY */
0059 #define MIPI_DPHY_D_LANES               2
0060 #define MIPI_DPHY_DEFAULT_BIT_RATES         63
0061
0062 #define KMB_MIPI_DEFAULT_CLK                24000000
0063 #define KMB_MIPI_DEFAULT_CFG_CLK            24000000
0064
0065 #define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base)
0066
0067 struct kmb_dsi {
0068     struct drm_encoder base;
0069     struct device *dev;
0070     struct platform_device *pdev;
0071     struct mipi_dsi_host *host;
0072     struct mipi_dsi_device *device;
0073     struct drm_bridge *adv_bridge;
0074     void __iomem *mipi_mmio;
0075     struct clk *clk_mipi;
0076     struct clk *clk_mipi_ecfg;
0077     struct clk *clk_mipi_cfg;
0078     int sys_clk_mhz;
0079 };
0080
0081 /* DPHY Tx test codes */
0082
0083 enum mipi_ctrl_num {
0084     MIPI_CTRL0 = 0,
0085     MIPI_CTRL1,
0086     MIPI_CTRL2,
0087     MIPI_CTRL3,
0088     MIPI_CTRL4,
0089     MIPI_CTRL5,
0090     MIPI_CTRL6,
0091     MIPI_CTRL7,
0092     MIPI_CTRL8,
0093     MIPI_CTRL9,
0094     MIPI_CTRL_NA
0095 };
0096
0097 enum mipi_dphy_num {
0098     MIPI_DPHY0 = 0,
0099     MIPI_DPHY1,
0100     MIPI_DPHY2,
0101     MIPI_DPHY3,
0102     MIPI_DPHY4,
0103     MIPI_DPHY5,
0104     MIPI_DPHY6,
0105     MIPI_DPHY7,
0106     MIPI_DPHY8,
0107     MIPI_DPHY9,
0108     MIPI_DPHY_NA
0109 };
0110
0111 enum mipi_dir {
0112     MIPI_RX,
0113     MIPI_TX
0114 };
0115
0116 enum mipi_ctrl_type {
0117     MIPI_DSI,
0118     MIPI_CSI
0119 };
0120
0121 enum mipi_data_if {
0122     MIPI_IF_DMA,
0123     MIPI_IF_PARALLEL
0124 };
0125
0126 enum mipi_data_mode {
0127     MIPI_DATA_MODE0,
0128     MIPI_DATA_MODE1,
0129     MIPI_DATA_MODE2,
0130     MIPI_DATA_MODE3
0131 };
0132
0133 enum mipi_dsi_video_mode {
0134     DSI_VIDEO_MODE_NO_BURST_PULSE,
0135     DSI_VIDEO_MODE_NO_BURST_EVENT,
0136     DSI_VIDEO_MODE_BURST
0137 };
0138
0139 enum mipi_dsi_blanking_mode {
0140     TRANSITION_TO_LOW_POWER,
0141     SEND_BLANK_PACKET
0142 };
0143
0144 enum mipi_dsi_eotp {
0145     DSI_EOTP_DISABLED,
0146     DSI_EOTP_ENABLES
0147 };
0148
0149 enum mipi_dsi_data_type {
0150     DSI_SP_DT_RESERVED_00 = 0x00,
0151     DSI_SP_DT_VSYNC_START = 0x01,
0152     DSI_SP_DT_COLOR_MODE_OFF = 0x02,
0153     DSI_SP_DT_GENERIC_SHORT_WR = 0x03,
0154     DSI_SP_DT_GENERIC_RD = 0x04,
0155     DSI_SP_DT_DCS_SHORT_WR = 0x05,
0156     DSI_SP_DT_DCS_RD = 0x06,
0157     DSI_SP_DT_EOTP = 0x08,
0158     DSI_LP_DT_NULL = 0x09,
0159     DSI_LP_DT_RESERVED_0A = 0x0a,
0160     DSI_LP_DT_RESERVED_0B = 0x0b,
0161     DSI_LP_DT_LPPS_YCBCR422_20B = 0x0c,
0162     DSI_LP_DT_PPS_RGB101010_30B = 0x0d,
0163     DSI_LP_DT_PPS_RGB565_16B = 0x0e,
0164     DSI_LP_DT_RESERVED_0F = 0x0f,
0165
0166     DSI_SP_DT_RESERVED_10 = 0x10,
0167     DSI_SP_DT_VSYNC_END = 0x11,
0168     DSI_SP_DT_COLOR_MODE_ON = 0x12,
0169     DSI_SP_DT_GENERIC_SHORT_WR_1PAR = 0x13,
0170     DSI_SP_DT_GENERIC_RD_1PAR = 0x14,
0171     DSI_SP_DT_DCS_SHORT_WR_1PAR = 0x15,
0172     DSI_SP_DT_RESERVED_16 = 0x16,
0173     DSI_SP_DT_RESERVED_17 = 0x17,
0174     DSI_SP_DT_RESERVED_18 = 0x18,
0175     DSI_LP_DT_BLANK = 0x19,
0176     DSI_LP_DT_RESERVED_1A = 0x1a,
0177     DSI_LP_DT_RESERVED_1B = 0x1b,
0178     DSI_LP_DT_PPS_YCBCR422_24B = 0x1c,
0179     DSI_LP_DT_PPS_RGB121212_36B = 0x1d,
0180     DSI_LP_DT_PPS_RGB666_18B = 0x1e,
0181     DSI_LP_DT_RESERVED_1F = 0x1f,
0182
0183     DSI_SP_DT_RESERVED_20 = 0x20,
0184     DSI_SP_DT_HSYNC_START = 0x21,
0185     DSI_SP_DT_SHUT_DOWN_PERIPH_CMD = 0x22,
0186     DSI_SP_DT_GENERIC_SHORT_WR_2PAR = 0x23,
0187     DSI_SP_DT_GENERIC_RD_2PAR = 0x24,
0188     DSI_SP_DT_RESERVED_25 = 0x25,
0189     DSI_SP_DT_RESERVED_26 = 0x26,
0190     DSI_SP_DT_RESERVED_27 = 0x27,
0191     DSI_SP_DT_RESERVED_28 = 0x28,
0192     DSI_LP_DT_GENERIC_LONG_WR = 0x29,
0193     DSI_LP_DT_RESERVED_2A = 0x2a,
0194     DSI_LP_DT_RESERVED_2B = 0x2b,
0195     DSI_LP_DT_PPS_YCBCR422_16B = 0x2c,
0196     DSI_LP_DT_RESERVED_2D = 0x2d,
0197     DSI_LP_DT_LPPS_RGB666_18B = 0x2e,
0198     DSI_LP_DT_RESERVED_2F = 0x2f,
0199
0200     DSI_SP_DT_RESERVED_30 = 0x30,
0201     DSI_SP_DT_HSYNC_END = 0x31,
0202     DSI_SP_DT_TURN_ON_PERIPH_CMD = 0x32,
0203     DSI_SP_DT_RESERVED_33 = 0x33,
0204     DSI_SP_DT_RESERVED_34 = 0x34,
0205     DSI_SP_DT_RESERVED_35 = 0x35,
0206     DSI_SP_DT_RESERVED_36 = 0x36,
0207     DSI_SP_DT_SET_MAX_RETURN_PKT_SIZE = 0x37,
0208     DSI_SP_DT_RESERVED_38 = 0x38,
0209     DSI_LP_DT_DSC_LONG_WR = 0x39,
0210     DSI_LP_DT_RESERVED_3A = 0x3a,
0211     DSI_LP_DT_RESERVED_3B = 0x3b,
0212     DSI_LP_DT_RESERVED_3C = 0x3c,
0213     DSI_LP_DT_PPS_YCBCR420_12B = 0x3d,
0214     DSI_LP_DT_PPS_RGB888_24B = 0x3e,
0215     DSI_LP_DT_RESERVED_3F = 0x3f
0216 };
0217
0218 enum mipi_tx_hs_tp_sel {
0219     MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0 = 0,
0220     MIPI_TX_HS_TP_WHOLE_FRAME_COLOR1,
0221     MIPI_TX_HS_TP_V_STRIPES,
0222     MIPI_TX_HS_TP_H_STRIPES,
0223 };
0224
0225 enum dphy_mode {
0226     MIPI_DPHY_SLAVE = 0,
0227     MIPI_DPHY_MASTER
0228 };
0229
0230 enum dphy_tx_fsm {
0231     DPHY_TX_POWERDWN = 0,
0232     DPHY_TX_BGPON,
0233     DPHY_TX_TERMCAL,
0234     DPHY_TX_TERMCALUP,
0235     DPHY_TX_OFFSETCAL,
0236     DPHY_TX_LOCK,
0237     DPHY_TX_SRCAL,
0238     DPHY_TX_IDLE,
0239     DPHY_TX_ULP,
0240     DPHY_TX_LANESTART,
0241     DPHY_TX_CLKALIGN,
0242     DPHY_TX_DDLTUNNING,
0243     DPHY_TX_ULP_FORCE_PLL,
0244     DPHY_TX_LOCK_LOSS
0245 };
0246
0247 struct mipi_data_type_params {
0248     u8 size_constraint_pixels;
0249     u8 size_constraint_bytes;
0250     u8 pixels_per_pclk;
0251     u8 bits_per_pclk;
0252 };
0253
0254 struct mipi_tx_dsi_cfg {
0255     u8 hfp_blank_en;    /* Horizontal front porch blanking enable */
0256     u8 eotp_en;     /* End of transmission packet enable */
0257     /* Last vertical front porch blanking mode */
0258     u8 lpm_last_vfp_line;
0259     /* First vertical sync active blanking mode */
0260     u8 lpm_first_vsa_line;
0261     u8 sync_pulse_eventn;   /* Sync type */
0262     u8 hfp_blanking;    /* Horizontal front porch blanking mode */
0263     u8 hbp_blanking;    /* Horizontal back porch blanking mode */
0264     u8 hsa_blanking;    /* Horizontal sync active blanking mode */
0265     u8 v_blanking;      /* Vertical timing blanking mode */
0266 };
0267
0268 struct mipi_tx_frame_section_cfg {
0269     u32 dma_v_stride;
0270     u16 dma_v_scale_cfg;
0271     u16 width_pixels;
0272     u16 height_lines;
0273     u8 dma_packed;
0274     u8 bpp;
0275     u8 bpp_unpacked;
0276     u8 dma_h_stride;
0277     u8 data_type;
0278     u8 data_mode;
0279     u8 dma_flip_rotate_sel;
0280 };
0281
0282 struct mipi_tx_frame_timing_cfg {
0283     u32 bpp;
0284     u32 lane_rate_mbps;
0285     u32 hsync_width;
0286     u32 h_backporch;
0287     u32 h_frontporch;
0288     u32 h_active;
0289     u16 vsync_width;
0290     u16 v_backporch;
0291     u16 v_frontporch;
0292     u16 v_active;
0293     u8 active_lanes;
0294 };
0295
0296 struct mipi_tx_frame_sect_phcfg {
0297     u32 wc;
0298     enum mipi_data_mode data_mode;
0299     enum mipi_dsi_data_type data_type;
0300     u8 vchannel;
0301     u8 dma_packed;
0302 };
0303
0304 struct mipi_tx_frame_cfg {
0305     struct mipi_tx_frame_section_cfg *sections[MIPI_TX_FRAME_GEN_SECTIONS];
0306     u32 hsync_width;    /* in pixels */
0307     u32 h_backporch;    /* in pixels */
0308     u32 h_frontporch;   /* in pixels */
0309     u16 vsync_width;    /* in lines */
0310     u16 v_backporch;    /* in lines */
0311     u16 v_frontporch;   /* in lines */
0312 };
0313
0314 struct mipi_tx_ctrl_cfg {
0315     struct mipi_tx_frame_cfg *frames[MIPI_TX_FRAME_GEN];
0316     const struct mipi_tx_dsi_cfg *tx_dsi_cfg;
0317     u8 line_sync_pkt_en;
0318     u8 line_counter_active;
0319     u8 frame_counter_active;
0320     u8 tx_hsclkkidle_cnt;
0321     u8 tx_hsexit_cnt;
0322     u8 tx_crc_en;
0323     u8 tx_hact_wait_stop;
0324     u8 tx_always_use_hact;
0325     u8 tx_wait_trig;
0326     u8 tx_wait_all_sect;
0327 };
0328
0329 /* configuration structure for MIPI control */
0330 struct mipi_ctrl_cfg {
0331     u8 active_lanes;    /* # active lanes per controller 2/4 */
0332     u32 lane_rate_mbps; /* MBPS */
0333     u32 ref_clk_khz;
0334     u32 cfg_clk_khz;
0335     struct mipi_tx_ctrl_cfg tx_ctrl_cfg;
0336 };
0337
0338 static inline void kmb_write_mipi(struct kmb_dsi *kmb_dsi,
0339                   unsigned int reg, u32 value)
0340 {
0341     writel(value, (kmb_dsi->mipi_mmio + reg));
0342 }
0343
0344 static inline u32 kmb_read_mipi(struct kmb_dsi *kmb_dsi, unsigned int reg)
0345 {
0346     return readl(kmb_dsi->mipi_mmio + reg);
0347 }
0348
0349 static inline void kmb_write_bits_mipi(struct kmb_dsi *kmb_dsi,
0350                        unsigned int reg, u32 offset,
0351                        u32 num_bits, u32 value)
0352 {
0353     u32 reg_val = kmb_read_mipi(kmb_dsi, reg);
0354     u32 mask = (1 << num_bits) - 1;
0355
0356     value &= mask;
0357     mask <<= offset;
0358     reg_val &= (~mask);
0359     reg_val |= (value << offset);
0360     kmb_write_mipi(kmb_dsi, reg, reg_val);
0361 }
0362
0363 static inline void kmb_set_bit_mipi(struct kmb_dsi *kmb_dsi,
0364                     unsigned int reg, u32 offset)
0365 {
0366     u32 reg_val = kmb_read_mipi(kmb_dsi, reg);
0367
0368     kmb_write_mipi(kmb_dsi, reg, reg_val | (1 << offset));
0369 }
0370
0371 static inline void kmb_clr_bit_mipi(struct kmb_dsi *kmb_dsi,
0372                     unsigned int reg, u32 offset)
0373 {
0374     u32 reg_val = kmb_read_mipi(kmb_dsi, reg);
0375
0376     kmb_write_mipi(kmb_dsi, reg, reg_val & (~(1 << offset)));
0377 }
0378
0379 int kmb_dsi_host_bridge_init(struct device *dev);
0380 struct kmb_dsi *kmb_dsi_init(struct platform_device *pdev);
0381 void kmb_dsi_host_unregister(struct kmb_dsi *kmb_dsi);
0382 int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
0383              int sys_clk_mhz, struct drm_atomic_state *old_state);
0384 int kmb_dsi_map_mmio(struct kmb_dsi *kmb_dsi);
0385 int kmb_dsi_clk_init(struct kmb_dsi *kmb_dsi);
0386 int kmb_dsi_encoder_init(struct drm_device *dev, struct kmb_dsi *kmb_dsi);
0387 #endif /* __KMB_DSI_H__ */