drm/kmb/kmb_drv.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  *
0003  * Copyright © 2018-2020 Intel Corporation
0004  */
0005
0006 #ifndef __KMB_DRV_H__
0007 #define __KMB_DRV_H__
0008
0009 #include <drm/drm_device.h>
0010
0011 #include "kmb_plane.h"
0012 #include "kmb_regs.h"
0013
0014 #define KMB_MAX_WIDTH           1920 /*Max width in pixels */
0015 #define KMB_MAX_HEIGHT          1080 /*Max height in pixels */
0016 #define KMB_MIN_WIDTH                   1920 /*Max width in pixels */
0017 #define KMB_MIN_HEIGHT                  1080 /*Max height in pixels */
0018
0019 #define DRIVER_DATE         "20210223"
0020 #define DRIVER_MAJOR            1
0021 #define DRIVER_MINOR            1
0022
0023 /* Platform definitions */
0024 #define KMB_CRTC_MIN_VFP        4
0025 #define KMB_CRTC_MAX_WIDTH      1920 /* max width in pixels */
0026 #define KMB_CRTC_MAX_HEIGHT     1080 /* max height in pixels */
0027 #define KMB_CRTC_MIN_WIDTH      1920
0028 #define KMB_CRTC_MIN_HEIGHT     1080
0029 #define KMB_FB_MAX_WIDTH        1920
0030 #define KMB_FB_MAX_HEIGHT       1080
0031 #define KMB_FB_MIN_WIDTH        1
0032 #define KMB_FB_MIN_HEIGHT       1
0033 #define KMB_MIN_VREFRESH        59    /*vertical refresh in Hz */
0034 #define KMB_MAX_VREFRESH        60    /*vertical refresh in Hz */
0035 #define KMB_LCD_DEFAULT_CLK     200000000
0036 #define KMB_SYS_CLK_MHZ         500
0037
0038 #define ICAM_MMIO       0x3b100000
0039 #define ICAM_LCD_OFFSET     0x1080
0040 #define ICAM_MMIO_SIZE      0x2000
0041
0042 struct kmb_dsi;
0043
0044 struct kmb_clock {
0045     struct clk *clk_lcd;
0046     struct clk *clk_pll0;
0047 };
0048
0049 struct kmb_drm_private {
0050     struct drm_device       drm;
0051     struct kmb_dsi          *kmb_dsi;
0052     void __iomem            *lcd_mmio;
0053     struct kmb_clock        kmb_clk;
0054     struct drm_crtc         crtc;
0055     struct kmb_plane        *plane;
0056     struct drm_atomic_state     *state;
0057     spinlock_t          irq_lock;
0058     int             irq_lcd;
0059     int             sys_clk_mhz;
0060     struct disp_cfg         init_disp_cfg[KMB_MAX_PLANES];
0061     struct layer_status     plane_status[KMB_MAX_PLANES];
0062     int             kmb_under_flow;
0063     int             kmb_flush_done;
0064     int             layer_no;
0065 };
0066
0067 static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev)
0068 {
0069     return container_of(dev, struct kmb_drm_private, drm);
0070 }
0071
0072 static inline struct kmb_drm_private *crtc_to_kmb_priv(const struct drm_crtc *x)
0073 {
0074     return container_of(x, struct kmb_drm_private, crtc);
0075 }
0076
0077 static inline void kmb_write_lcd(struct kmb_drm_private *dev_p,
0078                  unsigned int reg, u32 value)
0079 {
0080     writel(value, (dev_p->lcd_mmio + reg));
0081 }
0082
0083 static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg)
0084 {
0085     return readl(dev_p->lcd_mmio + reg);
0086 }
0087
0088 static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p,
0089                        unsigned int reg, u32 mask)
0090 {
0091     u32 reg_val = kmb_read_lcd(dev_p, reg);
0092
0093     kmb_write_lcd(dev_p, reg, (reg_val | mask));
0094 }
0095
0096 static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p,
0097                        unsigned int reg, u32 mask)
0098 {
0099     u32 reg_val = kmb_read_lcd(dev_p, reg);
0100
0101     kmb_write_lcd(dev_p, reg, (reg_val & (~mask)));
0102 }
0103
0104 int kmb_setup_crtc(struct drm_device *dev);
0105 void kmb_set_scanout(struct kmb_drm_private *lcd);
0106 #endif /* __KMB_DRV_H__ */