drm/kmb/kmb_crtc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright © 2018-2020 Intel Corporation
0004  */
0005
0006 #include <linux/clk.h>
0007
0008 #include <drm/drm_atomic.h>
0009 #include <drm/drm_atomic_helper.h>
0010 #include <drm/drm_crtc.h>
0011 #include <drm/drm_crtc_helper.h>
0012 #include <drm/drm_print.h>
0013 #include <drm/drm_vblank.h>
0014 #include <drm/drm_modeset_helper_vtables.h>
0015
0016 #include "kmb_drv.h"
0017 #include "kmb_dsi.h"
0018 #include "kmb_plane.h"
0019 #include "kmb_regs.h"
0020
0021 struct kmb_crtc_timing {
0022     u32 vfront_porch;
0023     u32 vback_porch;
0024     u32 vsync_len;
0025     u32 hfront_porch;
0026     u32 hback_porch;
0027     u32 hsync_len;
0028 };
0029
0030 static int kmb_crtc_enable_vblank(struct drm_crtc *crtc)
0031 {
0032     struct drm_device *dev = crtc->dev;
0033     struct kmb_drm_private *kmb = to_kmb(dev);
0034
0035     /* Clear interrupt */
0036     kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
0037     /* Set which interval to generate vertical interrupt */
0038     kmb_write_lcd(kmb, LCD_VSTATUS_COMPARE,
0039               LCD_VSTATUS_COMPARE_VSYNC);
0040     /* Enable vertical interrupt */
0041     kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE,
0042                 LCD_INT_VERT_COMP);
0043     return 0;
0044 }
0045
0046 static void kmb_crtc_disable_vblank(struct drm_crtc *crtc)
0047 {
0048     struct drm_device *dev = crtc->dev;
0049     struct kmb_drm_private *kmb = to_kmb(dev);
0050
0051     /* Clear interrupt */
0052     kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
0053     /* Disable vertical interrupt */
0054     kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
0055                 LCD_INT_VERT_COMP);
0056 }
0057
0058 static const struct drm_crtc_funcs kmb_crtc_funcs = {
0059     .destroy = drm_crtc_cleanup,
0060     .set_config = drm_atomic_helper_set_config,
0061     .page_flip = drm_atomic_helper_page_flip,
0062     .reset = drm_atomic_helper_crtc_reset,
0063     .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
0064     .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
0065     .enable_vblank = kmb_crtc_enable_vblank,
0066     .disable_vblank = kmb_crtc_disable_vblank,
0067 };
0068
0069 static void kmb_crtc_set_mode(struct drm_crtc *crtc,
0070                   struct drm_atomic_state *old_state)
0071 {
0072     struct drm_device *dev = crtc->dev;
0073     struct drm_display_mode *m = &crtc->state->adjusted_mode;
0074     struct kmb_crtc_timing vm;
0075     struct kmb_drm_private *kmb = to_kmb(dev);
0076     unsigned int val = 0;
0077
0078     /* Initialize mipi */
0079     kmb_dsi_mode_set(kmb->kmb_dsi, m, kmb->sys_clk_mhz, old_state);
0080     drm_info(dev,
0081          "vfp= %d vbp= %d vsync_len=%d hfp=%d hbp=%d hsync_len=%d\n",
0082          m->crtc_vsync_start - m->crtc_vdisplay,
0083          m->crtc_vtotal - m->crtc_vsync_end,
0084          m->crtc_vsync_end - m->crtc_vsync_start,
0085          m->crtc_hsync_start - m->crtc_hdisplay,
0086          m->crtc_htotal - m->crtc_hsync_end,
0087          m->crtc_hsync_end - m->crtc_hsync_start);
0088     val = kmb_read_lcd(kmb, LCD_INT_ENABLE);
0089     kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE, val);
0090     kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, ~0x0);
0091     vm.vfront_porch = 2;
0092     vm.vback_porch = 2;
0093     vm.vsync_len = 8;
0094     vm.hfront_porch = 0;
0095     vm.hback_porch = 0;
0096     vm.hsync_len = 28;
0097
0098     drm_dbg(dev, "%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hsync-l=%d",
0099         __func__, __LINE__,
0100             m->crtc_vdisplay, vm.vback_porch, vm.vfront_porch,
0101             vm.vsync_len, m->crtc_hdisplay, vm.hback_porch,
0102             vm.hfront_porch, vm.hsync_len);
0103     kmb_write_lcd(kmb, LCD_V_ACTIVEHEIGHT,
0104               m->crtc_vdisplay - 1);
0105     kmb_write_lcd(kmb, LCD_V_BACKPORCH, vm.vback_porch);
0106     kmb_write_lcd(kmb, LCD_V_FRONTPORCH, vm.vfront_porch);
0107     kmb_write_lcd(kmb, LCD_VSYNC_WIDTH, vm.vsync_len - 1);
0108     kmb_write_lcd(kmb, LCD_H_ACTIVEWIDTH,
0109               m->crtc_hdisplay - 1);
0110     kmb_write_lcd(kmb, LCD_H_BACKPORCH, vm.hback_porch);
0111     kmb_write_lcd(kmb, LCD_H_FRONTPORCH, vm.hfront_porch);
0112     kmb_write_lcd(kmb, LCD_HSYNC_WIDTH, vm.hsync_len - 1);
0113     /* This is hardcoded as 0 in the Myriadx code */
0114     kmb_write_lcd(kmb, LCD_VSYNC_START, 0);
0115     kmb_write_lcd(kmb, LCD_VSYNC_END, 0);
0116     /* Back ground color */
0117     kmb_write_lcd(kmb, LCD_BG_COLOUR_LS, 0x4);
0118     if (m->flags == DRM_MODE_FLAG_INTERLACE) {
0119         kmb_write_lcd(kmb,
0120                   LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
0121         kmb_write_lcd(kmb,
0122                   LCD_V_BACKPORCH_EVEN, vm.vback_porch);
0123         kmb_write_lcd(kmb,
0124                   LCD_V_FRONTPORCH_EVEN, vm.vfront_porch);
0125         kmb_write_lcd(kmb, LCD_V_ACTIVEHEIGHT_EVEN,
0126                   m->crtc_vdisplay - 1);
0127         /* This is hardcoded as 10 in the Myriadx code */
0128         kmb_write_lcd(kmb, LCD_VSYNC_START_EVEN, 10);
0129         kmb_write_lcd(kmb, LCD_VSYNC_END_EVEN, 10);
0130     }
0131     kmb_write_lcd(kmb, LCD_TIMING_GEN_TRIG, 1);
0132     kmb_set_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_ENABLE);
0133     kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE, val);
0134 }
0135
0136 static void kmb_crtc_atomic_enable(struct drm_crtc *crtc,
0137                    struct drm_atomic_state *state)
0138 {
0139     struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc);
0140
0141     clk_prepare_enable(kmb->kmb_clk.clk_lcd);
0142     kmb_crtc_set_mode(crtc, state);
0143     drm_crtc_vblank_on(crtc);
0144 }
0145
0146 static void kmb_crtc_atomic_disable(struct drm_crtc *crtc,
0147                     struct drm_atomic_state *state)
0148 {
0149     struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc);
0150     struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
0151
0152     /* due to hw limitations, planes need to be off when crtc is off */
0153     drm_atomic_helper_disable_planes_on_crtc(old_state, false);
0154
0155     drm_crtc_vblank_off(crtc);
0156     clk_disable_unprepare(kmb->kmb_clk.clk_lcd);
0157 }
0158
0159 static void kmb_crtc_atomic_begin(struct drm_crtc *crtc,
0160                   struct drm_atomic_state *state)
0161 {
0162     struct drm_device *dev = crtc->dev;
0163     struct kmb_drm_private *kmb = to_kmb(dev);
0164
0165     kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
0166                 LCD_INT_VERT_COMP);
0167 }
0168
0169 static void kmb_crtc_atomic_flush(struct drm_crtc *crtc,
0170                   struct drm_atomic_state *state)
0171 {
0172     struct drm_device *dev = crtc->dev;
0173     struct kmb_drm_private *kmb = to_kmb(dev);
0174
0175     kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE,
0176                 LCD_INT_VERT_COMP);
0177
0178     spin_lock_irq(&crtc->dev->event_lock);
0179     if (crtc->state->event) {
0180         if (drm_crtc_vblank_get(crtc) == 0)
0181             drm_crtc_arm_vblank_event(crtc, crtc->state->event);
0182         else
0183             drm_crtc_send_vblank_event(crtc, crtc->state->event);
0184     }
0185     crtc->state->event = NULL;
0186     spin_unlock_irq(&crtc->dev->event_lock);
0187 }
0188
0189 static enum drm_mode_status
0190         kmb_crtc_mode_valid(struct drm_crtc *crtc,
0191                     const struct drm_display_mode *mode)
0192 {
0193     int refresh;
0194     struct drm_device *dev = crtc->dev;
0195     int vfp = mode->vsync_start - mode->vdisplay;
0196
0197     if (mode->vdisplay < KMB_CRTC_MAX_HEIGHT) {
0198         drm_dbg(dev, "height = %d less than %d",
0199             mode->vdisplay, KMB_CRTC_MAX_HEIGHT);
0200         return MODE_BAD_VVALUE;
0201     }
0202     if (mode->hdisplay < KMB_CRTC_MAX_WIDTH) {
0203         drm_dbg(dev, "width = %d less than %d",
0204             mode->hdisplay, KMB_CRTC_MAX_WIDTH);
0205         return MODE_BAD_HVALUE;
0206     }
0207     refresh = drm_mode_vrefresh(mode);
0208     if (refresh < KMB_MIN_VREFRESH || refresh > KMB_MAX_VREFRESH) {
0209         drm_dbg(dev, "refresh = %d less than %d or greater than %d",
0210             refresh, KMB_MIN_VREFRESH, KMB_MAX_VREFRESH);
0211         return MODE_BAD;
0212     }
0213
0214     if (vfp < KMB_CRTC_MIN_VFP) {
0215         drm_dbg(dev, "vfp = %d less than %d", vfp, KMB_CRTC_MIN_VFP);
0216         return MODE_BAD;
0217     }
0218
0219     return MODE_OK;
0220 }
0221
0222 static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = {
0223     .atomic_begin = kmb_crtc_atomic_begin,
0224     .atomic_enable = kmb_crtc_atomic_enable,
0225     .atomic_disable = kmb_crtc_atomic_disable,
0226     .atomic_flush = kmb_crtc_atomic_flush,
0227     .mode_valid = kmb_crtc_mode_valid,
0228 };
0229
0230 int kmb_setup_crtc(struct drm_device *drm)
0231 {
0232     struct kmb_drm_private *kmb = to_kmb(drm);
0233     struct kmb_plane *primary;
0234     int ret;
0235
0236     primary = kmb_plane_init(drm);
0237     if (IS_ERR(primary))
0238         return PTR_ERR(primary);
0239
0240     ret = drm_crtc_init_with_planes(drm, &kmb->crtc, &primary->base_plane,
0241                     NULL, &kmb_crtc_funcs, NULL);
0242     if (ret) {
0243         kmb_plane_destroy(&primary->base_plane);
0244         return ret;
0245     }
0246
0247     drm_crtc_helper_add(&kmb->crtc, &kmb_crtc_helper_funcs);
0248     return 0;
0249 }