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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Ingenic JZ47xx IPU driver
0004 //
0005 // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
0006 // Copyright (C) 2020, Daniel Silsby <dansilsby@gmail.com>
0007 
0008 #include "ingenic-drm.h"
0009 #include "ingenic-ipu.h"
0010 
0011 #include <linux/clk.h>
0012 #include <linux/component.h>
0013 #include <linux/gcd.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/regmap.h>
0019 #include <linux/time.h>
0020 
0021 #include <drm/drm_atomic.h>
0022 #include <drm/drm_atomic_helper.h>
0023 #include <drm/drm_damage_helper.h>
0024 #include <drm/drm_drv.h>
0025 #include <drm/drm_fb_cma_helper.h>
0026 #include <drm/drm_fourcc.h>
0027 #include <drm/drm_framebuffer.h>
0028 #include <drm/drm_gem_atomic_helper.h>
0029 #include <drm/drm_gem_cma_helper.h>
0030 #include <drm/drm_gem_framebuffer_helper.h>
0031 #include <drm/drm_plane.h>
0032 #include <drm/drm_plane_helper.h>
0033 #include <drm/drm_property.h>
0034 #include <drm/drm_vblank.h>
0035 
0036 struct ingenic_ipu;
0037 
0038 struct soc_info {
0039     const u32 *formats;
0040     size_t num_formats;
0041     bool has_bicubic;
0042     bool manual_restart;
0043 
0044     void (*set_coefs)(struct ingenic_ipu *ipu, unsigned int reg,
0045               unsigned int sharpness, bool downscale,
0046               unsigned int weight, unsigned int offset);
0047 };
0048 
0049 struct ingenic_ipu_private_state {
0050     struct drm_private_state base;
0051 
0052     unsigned int num_w, num_h, denom_w, denom_h;
0053 };
0054 
0055 struct ingenic_ipu {
0056     struct drm_plane plane;
0057     struct drm_device *drm;
0058     struct device *dev, *master;
0059     struct regmap *map;
0060     struct clk *clk;
0061     const struct soc_info *soc_info;
0062     bool clk_enabled;
0063 
0064     dma_addr_t addr_y, addr_u, addr_v;
0065 
0066     struct drm_property *sharpness_prop;
0067     unsigned int sharpness;
0068 
0069     struct drm_private_obj private_obj;
0070 };
0071 
0072 /* Signed 15.16 fixed-point math (for bicubic scaling coefficients) */
0073 #define I2F(i) ((s32)(i) * 65536)
0074 #define F2I(f) ((f) / 65536)
0075 #define FMUL(fa, fb) ((s32)(((s64)(fa) * (s64)(fb)) / 65536))
0076 #define SHARPNESS_INCR (I2F(-1) / 8)
0077 
0078 static inline struct ingenic_ipu *plane_to_ingenic_ipu(struct drm_plane *plane)
0079 {
0080     return container_of(plane, struct ingenic_ipu, plane);
0081 }
0082 
0083 static inline struct ingenic_ipu_private_state *
0084 to_ingenic_ipu_priv_state(struct drm_private_state *state)
0085 {
0086     return container_of(state, struct ingenic_ipu_private_state, base);
0087 }
0088 
0089 static struct ingenic_ipu_private_state *
0090 ingenic_ipu_get_priv_state(struct ingenic_ipu *priv, struct drm_atomic_state *state)
0091 {
0092     struct drm_private_state *priv_state;
0093 
0094     priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj);
0095     if (IS_ERR(priv_state))
0096         return ERR_CAST(priv_state);
0097 
0098     return to_ingenic_ipu_priv_state(priv_state);
0099 }
0100 
0101 static struct ingenic_ipu_private_state *
0102 ingenic_ipu_get_new_priv_state(struct ingenic_ipu *priv, struct drm_atomic_state *state)
0103 {
0104     struct drm_private_state *priv_state;
0105 
0106     priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj);
0107     if (!priv_state)
0108         return NULL;
0109 
0110     return to_ingenic_ipu_priv_state(priv_state);
0111 }
0112 
0113 /*
0114  * Apply conventional cubic convolution kernel. Both parameters
0115  *  and return value are 15.16 signed fixed-point.
0116  *
0117  *  @f_a: Sharpness factor, typically in range [-4.0, -0.25].
0118  *        A larger magnitude increases perceived sharpness, but going past
0119  *        -2.0 might cause ringing artifacts to outweigh any improvement.
0120  *        Nice values on a 320x240 LCD are between -0.75 and -2.0.
0121  *
0122  *  @f_x: Absolute distance in pixels from 'pixel 0' sample position
0123  *        along horizontal (or vertical) source axis. Range is [0, +2.0].
0124  *
0125  *  returns: Weight of this pixel within 4-pixel sample group. Range is
0126  *           [-2.0, +2.0]. For moderate (i.e. > -3.0) sharpness factors,
0127  *           range is within [-1.0, +1.0].
0128  */
0129 static inline s32 cubic_conv(s32 f_a, s32 f_x)
0130 {
0131     const s32 f_1 = I2F(1);
0132     const s32 f_2 = I2F(2);
0133     const s32 f_3 = I2F(3);
0134     const s32 f_4 = I2F(4);
0135     const s32 f_x2 = FMUL(f_x, f_x);
0136     const s32 f_x3 = FMUL(f_x, f_x2);
0137 
0138     if (f_x <= f_1)
0139         return FMUL((f_a + f_2), f_x3) - FMUL((f_a + f_3), f_x2) + f_1;
0140     else if (f_x <= f_2)
0141         return FMUL(f_a, (f_x3 - 5 * f_x2 + 8 * f_x - f_4));
0142     else
0143         return 0;
0144 }
0145 
0146 /*
0147  * On entry, "weight" is a coefficient suitable for bilinear mode,
0148  *  which is converted to a set of four suitable for bicubic mode.
0149  *
0150  * "weight 512" means all of pixel 0;
0151  * "weight 256" means half of pixel 0 and half of pixel 1;
0152  * "weight 0" means all of pixel 1;
0153  *
0154  * "offset" is increment to next source pixel sample location.
0155  */
0156 static void jz4760_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
0157                  unsigned int sharpness, bool downscale,
0158                  unsigned int weight, unsigned int offset)
0159 {
0160     u32 val;
0161     s32 w0, w1, w2, w3; /* Pixel weights at X (or Y) offsets -1,0,1,2 */
0162 
0163     weight = clamp_val(weight, 0, 512);
0164 
0165     if (sharpness < 2) {
0166         /*
0167          *  When sharpness setting is 0, emulate nearest-neighbor.
0168          *  When sharpness setting is 1, emulate bilinear.
0169          */
0170 
0171         if (sharpness == 0)
0172             weight = weight >= 256 ? 512 : 0;
0173         w0 = 0;
0174         w1 = weight;
0175         w2 = 512 - weight;
0176         w3 = 0;
0177     } else {
0178         const s32 f_a = SHARPNESS_INCR * sharpness;
0179         const s32 f_h = I2F(1) / 2; /* Round up 0.5 */
0180 
0181         /*
0182          * Note that always rounding towards +infinity here is intended.
0183          * The resulting coefficients match a round-to-nearest-int
0184          * double floating-point implementation.
0185          */
0186 
0187         weight = 512 - weight;
0188         w0 = F2I(f_h + 512 * cubic_conv(f_a, I2F(512  + weight) / 512));
0189         w1 = F2I(f_h + 512 * cubic_conv(f_a, I2F(0    + weight) / 512));
0190         w2 = F2I(f_h + 512 * cubic_conv(f_a, I2F(512  - weight) / 512));
0191         w3 = F2I(f_h + 512 * cubic_conv(f_a, I2F(1024 - weight) / 512));
0192         w0 = clamp_val(w0, -1024, 1023);
0193         w1 = clamp_val(w1, -1024, 1023);
0194         w2 = clamp_val(w2, -1024, 1023);
0195         w3 = clamp_val(w3, -1024, 1023);
0196     }
0197 
0198     val = ((w1 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF31_LSB) |
0199         ((w0 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF20_LSB);
0200     regmap_write(ipu->map, reg, val);
0201 
0202     val = ((w3 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF31_LSB) |
0203         ((w2 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF20_LSB) |
0204         ((offset & JZ4760_IPU_RSZ_OFFSET_MASK) << JZ4760_IPU_RSZ_OFFSET_LSB);
0205     regmap_write(ipu->map, reg, val);
0206 }
0207 
0208 static void jz4725b_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
0209                   unsigned int sharpness, bool downscale,
0210                   unsigned int weight, unsigned int offset)
0211 {
0212     u32 val = JZ4725B_IPU_RSZ_LUT_OUT_EN;
0213     unsigned int i;
0214 
0215     weight = clamp_val(weight, 0, 512);
0216 
0217     if (sharpness == 0)
0218         weight = weight >= 256 ? 512 : 0;
0219 
0220     val |= (weight & JZ4725B_IPU_RSZ_LUT_COEF_MASK) << JZ4725B_IPU_RSZ_LUT_COEF_LSB;
0221     if (downscale || !!offset)
0222         val |= JZ4725B_IPU_RSZ_LUT_IN_EN;
0223 
0224     regmap_write(ipu->map, reg, val);
0225 
0226     if (downscale) {
0227         for (i = 1; i < offset; i++)
0228             regmap_write(ipu->map, reg, JZ4725B_IPU_RSZ_LUT_IN_EN);
0229     }
0230 }
0231 
0232 static void ingenic_ipu_set_downscale_coefs(struct ingenic_ipu *ipu,
0233                         unsigned int reg,
0234                         unsigned int num,
0235                         unsigned int denom)
0236 {
0237     unsigned int i, offset, weight, weight_num = denom;
0238 
0239     for (i = 0; i < num; i++) {
0240         weight_num = num + (weight_num - num) % (num * 2);
0241         weight = 512 - 512 * (weight_num - num) / (num * 2);
0242         weight_num += denom * 2;
0243         offset = (weight_num - num) / (num * 2);
0244 
0245         ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
0246                      true, weight, offset);
0247     }
0248 }
0249 
0250 static void ingenic_ipu_set_integer_upscale_coefs(struct ingenic_ipu *ipu,
0251                           unsigned int reg,
0252                           unsigned int num)
0253 {
0254     /*
0255      * Force nearest-neighbor scaling and use simple math when upscaling
0256      * by an integer ratio. It looks better, and fixes a few problem cases.
0257      */
0258     unsigned int i;
0259 
0260     for (i = 0; i < num; i++)
0261         ipu->soc_info->set_coefs(ipu, reg, 0, false, 512, i == num - 1);
0262 }
0263 
0264 static void ingenic_ipu_set_upscale_coefs(struct ingenic_ipu *ipu,
0265                       unsigned int reg,
0266                       unsigned int num,
0267                       unsigned int denom)
0268 {
0269     unsigned int i, offset, weight, weight_num = 0;
0270 
0271     for (i = 0; i < num; i++) {
0272         weight = 512 - 512 * weight_num / num;
0273         weight_num += denom;
0274         offset = weight_num >= num;
0275 
0276         if (offset)
0277             weight_num -= num;
0278 
0279         ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
0280                      false, weight, offset);
0281     }
0282 }
0283 
0284 static void ingenic_ipu_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
0285                   unsigned int num, unsigned int denom)
0286 {
0287     /* Begin programming the LUT */
0288     regmap_write(ipu->map, reg, -1);
0289 
0290     if (denom > num)
0291         ingenic_ipu_set_downscale_coefs(ipu, reg, num, denom);
0292     else if (denom == 1)
0293         ingenic_ipu_set_integer_upscale_coefs(ipu, reg, num);
0294     else
0295         ingenic_ipu_set_upscale_coefs(ipu, reg, num, denom);
0296 }
0297 
0298 static int reduce_fraction(unsigned int *num, unsigned int *denom)
0299 {
0300     unsigned long d = gcd(*num, *denom);
0301 
0302     /* The scaling table has only 31 entries */
0303     if (*num > 31 * d)
0304         return -EINVAL;
0305 
0306     *num /= d;
0307     *denom /= d;
0308     return 0;
0309 }
0310 
0311 static inline bool osd_changed(struct drm_plane_state *state,
0312                    struct drm_plane_state *oldstate)
0313 {
0314     return state->src_x != oldstate->src_x ||
0315         state->src_y != oldstate->src_y ||
0316         state->src_w != oldstate->src_w ||
0317         state->src_h != oldstate->src_h ||
0318         state->crtc_x != oldstate->crtc_x ||
0319         state->crtc_y != oldstate->crtc_y ||
0320         state->crtc_w != oldstate->crtc_w ||
0321         state->crtc_h != oldstate->crtc_h;
0322 }
0323 
0324 static void ingenic_ipu_plane_atomic_update(struct drm_plane *plane,
0325                         struct drm_atomic_state *state)
0326 {
0327     struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
0328     struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane);
0329     struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane);
0330     const struct drm_format_info *finfo;
0331     u32 ctrl, stride = 0, coef_index = 0, format = 0;
0332     bool needs_modeset, upscaling_w, upscaling_h;
0333     struct ingenic_ipu_private_state *ipu_state;
0334     int err;
0335 
0336     if (!newstate || !newstate->fb)
0337         return;
0338 
0339     ipu_state = ingenic_ipu_get_new_priv_state(ipu, state);
0340     if (WARN_ON(!ipu_state))
0341         return;
0342 
0343     finfo = drm_format_info(newstate->fb->format->format);
0344 
0345     if (!ipu->clk_enabled) {
0346         err = clk_enable(ipu->clk);
0347         if (err) {
0348             dev_err(ipu->dev, "Unable to enable clock: %d\n", err);
0349             return;
0350         }
0351 
0352         ipu->clk_enabled = true;
0353     }
0354 
0355     /* Reset all the registers if needed */
0356     needs_modeset = drm_atomic_crtc_needs_modeset(newstate->crtc->state);
0357     if (needs_modeset) {
0358         regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RST);
0359 
0360         /* Enable the chip */
0361         regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
0362                 JZ_IPU_CTRL_CHIP_EN | JZ_IPU_CTRL_LCDC_SEL);
0363     }
0364 
0365     if (ingenic_drm_map_noncoherent(ipu->master))
0366         drm_fb_cma_sync_non_coherent(ipu->drm, oldstate, newstate);
0367 
0368     /* New addresses will be committed in vblank handler... */
0369     ipu->addr_y = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0);
0370     if (finfo->num_planes > 1)
0371         ipu->addr_u = drm_fb_cma_get_gem_addr(newstate->fb, newstate,
0372                               1);
0373     if (finfo->num_planes > 2)
0374         ipu->addr_v = drm_fb_cma_get_gem_addr(newstate->fb, newstate,
0375                               2);
0376 
0377     if (!needs_modeset)
0378         return;
0379 
0380     /* Or right here if we're doing a full modeset. */
0381     regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
0382     regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
0383     regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
0384 
0385     if (finfo->num_planes == 1)
0386         regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_SPKG_SEL);
0387 
0388     ingenic_drm_plane_config(ipu->master, plane, DRM_FORMAT_XRGB8888);
0389 
0390     /* Set the input height/width/strides */
0391     if (finfo->num_planes > 2)
0392         stride = ((newstate->src_w >> 16) * finfo->cpp[2] / finfo->hsub)
0393             << JZ_IPU_UV_STRIDE_V_LSB;
0394 
0395     if (finfo->num_planes > 1)
0396         stride |= ((newstate->src_w >> 16) * finfo->cpp[1] / finfo->hsub)
0397             << JZ_IPU_UV_STRIDE_U_LSB;
0398 
0399     regmap_write(ipu->map, JZ_REG_IPU_UV_STRIDE, stride);
0400 
0401     stride = ((newstate->src_w >> 16) * finfo->cpp[0]) << JZ_IPU_Y_STRIDE_Y_LSB;
0402     regmap_write(ipu->map, JZ_REG_IPU_Y_STRIDE, stride);
0403 
0404     regmap_write(ipu->map, JZ_REG_IPU_IN_GS,
0405              (stride << JZ_IPU_IN_GS_W_LSB) |
0406              ((newstate->src_h >> 16) << JZ_IPU_IN_GS_H_LSB));
0407 
0408     switch (finfo->format) {
0409     case DRM_FORMAT_XRGB1555:
0410         format = JZ_IPU_D_FMT_IN_FMT_RGB555 |
0411             JZ_IPU_D_FMT_RGB_OUT_OFT_RGB;
0412         break;
0413     case DRM_FORMAT_XBGR1555:
0414         format = JZ_IPU_D_FMT_IN_FMT_RGB555 |
0415             JZ_IPU_D_FMT_RGB_OUT_OFT_BGR;
0416         break;
0417     case DRM_FORMAT_RGB565:
0418         format = JZ_IPU_D_FMT_IN_FMT_RGB565 |
0419             JZ_IPU_D_FMT_RGB_OUT_OFT_RGB;
0420         break;
0421     case DRM_FORMAT_BGR565:
0422         format = JZ_IPU_D_FMT_IN_FMT_RGB565 |
0423             JZ_IPU_D_FMT_RGB_OUT_OFT_BGR;
0424         break;
0425     case DRM_FORMAT_XRGB8888:
0426     case DRM_FORMAT_XYUV8888:
0427         format = JZ_IPU_D_FMT_IN_FMT_RGB888 |
0428             JZ_IPU_D_FMT_RGB_OUT_OFT_RGB;
0429         break;
0430     case DRM_FORMAT_XBGR8888:
0431         format = JZ_IPU_D_FMT_IN_FMT_RGB888 |
0432             JZ_IPU_D_FMT_RGB_OUT_OFT_BGR;
0433         break;
0434     case DRM_FORMAT_YUYV:
0435         format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
0436             JZ_IPU_D_FMT_YUV_VY1UY0;
0437         break;
0438     case DRM_FORMAT_YVYU:
0439         format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
0440             JZ_IPU_D_FMT_YUV_UY1VY0;
0441         break;
0442     case DRM_FORMAT_UYVY:
0443         format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
0444             JZ_IPU_D_FMT_YUV_Y1VY0U;
0445         break;
0446     case DRM_FORMAT_VYUY:
0447         format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
0448             JZ_IPU_D_FMT_YUV_Y1UY0V;
0449         break;
0450     case DRM_FORMAT_YUV411:
0451         format = JZ_IPU_D_FMT_IN_FMT_YUV411;
0452         break;
0453     case DRM_FORMAT_YUV420:
0454         format = JZ_IPU_D_FMT_IN_FMT_YUV420;
0455         break;
0456     case DRM_FORMAT_YUV422:
0457         format = JZ_IPU_D_FMT_IN_FMT_YUV422;
0458         break;
0459     case DRM_FORMAT_YUV444:
0460         format = JZ_IPU_D_FMT_IN_FMT_YUV444;
0461         break;
0462     default:
0463         WARN_ONCE(1, "Unsupported format");
0464         break;
0465     }
0466 
0467     /* Fix output to RGB888 */
0468     format |= JZ_IPU_D_FMT_OUT_FMT_RGB888;
0469 
0470     /* Set pixel format */
0471     regmap_write(ipu->map, JZ_REG_IPU_D_FMT, format);
0472 
0473     /* Set the output height/width/stride */
0474     regmap_write(ipu->map, JZ_REG_IPU_OUT_GS,
0475              ((newstate->crtc_w * 4) << JZ_IPU_OUT_GS_W_LSB)
0476              | newstate->crtc_h << JZ_IPU_OUT_GS_H_LSB);
0477     regmap_write(ipu->map, JZ_REG_IPU_OUT_STRIDE, newstate->crtc_w * 4);
0478 
0479     if (finfo->is_yuv) {
0480         regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CSC_EN);
0481 
0482         /*
0483          * Offsets for Chroma/Luma.
0484          * y = source Y - LUMA,
0485          * u = source Cb - CHROMA,
0486          * v = source Cr - CHROMA
0487          */
0488         regmap_write(ipu->map, JZ_REG_IPU_CSC_OFFSET,
0489                  128 << JZ_IPU_CSC_OFFSET_CHROMA_LSB |
0490                  0 << JZ_IPU_CSC_OFFSET_LUMA_LSB);
0491 
0492         /*
0493          * YUV422 to RGB conversion table.
0494          * R = C0 / 0x400 * y + C1 / 0x400 * v
0495          * G = C0 / 0x400 * y - C2 / 0x400 * u - C3 / 0x400 * v
0496          * B = C0 / 0x400 * y + C4 / 0x400 * u
0497          */
0498         regmap_write(ipu->map, JZ_REG_IPU_CSC_C0_COEF, 0x4a8);
0499         regmap_write(ipu->map, JZ_REG_IPU_CSC_C1_COEF, 0x662);
0500         regmap_write(ipu->map, JZ_REG_IPU_CSC_C2_COEF, 0x191);
0501         regmap_write(ipu->map, JZ_REG_IPU_CSC_C3_COEF, 0x341);
0502         regmap_write(ipu->map, JZ_REG_IPU_CSC_C4_COEF, 0x811);
0503     }
0504 
0505     ctrl = 0;
0506 
0507     /*
0508      * Must set ZOOM_SEL before programming bicubic LUTs.
0509      * If the IPU supports bicubic, we enable it unconditionally, since it
0510      * can do anything bilinear can and more.
0511      */
0512     if (ipu->soc_info->has_bicubic)
0513         ctrl |= JZ_IPU_CTRL_ZOOM_SEL;
0514 
0515     upscaling_w = ipu_state->num_w > ipu_state->denom_w;
0516     if (upscaling_w)
0517         ctrl |= JZ_IPU_CTRL_HSCALE;
0518 
0519     if (ipu_state->num_w != 1 || ipu_state->denom_w != 1) {
0520         if (!ipu->soc_info->has_bicubic && !upscaling_w)
0521             coef_index |= (ipu_state->denom_w - 1) << 16;
0522         else
0523             coef_index |= (ipu_state->num_w - 1) << 16;
0524         ctrl |= JZ_IPU_CTRL_HRSZ_EN;
0525     }
0526 
0527     upscaling_h = ipu_state->num_h > ipu_state->denom_h;
0528     if (upscaling_h)
0529         ctrl |= JZ_IPU_CTRL_VSCALE;
0530 
0531     if (ipu_state->num_h != 1 || ipu_state->denom_h != 1) {
0532         if (!ipu->soc_info->has_bicubic && !upscaling_h)
0533             coef_index |= ipu_state->denom_h - 1;
0534         else
0535             coef_index |= ipu_state->num_h - 1;
0536         ctrl |= JZ_IPU_CTRL_VRSZ_EN;
0537     }
0538 
0539     regmap_update_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_ZOOM_SEL |
0540                JZ_IPU_CTRL_HRSZ_EN | JZ_IPU_CTRL_VRSZ_EN |
0541                JZ_IPU_CTRL_HSCALE | JZ_IPU_CTRL_VSCALE, ctrl);
0542 
0543     /* Set the LUT index register */
0544     regmap_write(ipu->map, JZ_REG_IPU_RSZ_COEF_INDEX, coef_index);
0545 
0546     if (ipu_state->num_w != 1 || ipu_state->denom_w != 1)
0547         ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_HRSZ_COEF_LUT,
0548                       ipu_state->num_w, ipu_state->denom_w);
0549 
0550     if (ipu_state->num_h != 1 || ipu_state->denom_h != 1)
0551         ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_VRSZ_COEF_LUT,
0552                       ipu_state->num_h, ipu_state->denom_h);
0553 
0554     /* Clear STATUS register */
0555     regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
0556 
0557     /* Start IPU */
0558     regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
0559             JZ_IPU_CTRL_RUN | JZ_IPU_CTRL_FM_IRQ_EN);
0560 
0561     dev_dbg(ipu->dev, "Scaling %ux%u to %ux%u (%u:%u horiz, %u:%u vert)\n",
0562         newstate->src_w >> 16, newstate->src_h >> 16,
0563         newstate->crtc_w, newstate->crtc_h,
0564         ipu_state->num_w, ipu_state->denom_w,
0565         ipu_state->num_h, ipu_state->denom_h);
0566 }
0567 
0568 static int ingenic_ipu_plane_atomic_check(struct drm_plane *plane,
0569                       struct drm_atomic_state *state)
0570 {
0571     struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
0572                                          plane);
0573     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
0574                                          plane);
0575     unsigned int num_w, denom_w, num_h, denom_h, xres, yres, max_w, max_h;
0576     struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
0577     struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
0578     struct drm_crtc_state *crtc_state;
0579     struct ingenic_ipu_private_state *ipu_state;
0580 
0581     if (!crtc)
0582         return 0;
0583 
0584     crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
0585     if (WARN_ON(!crtc_state))
0586         return -EINVAL;
0587 
0588     ipu_state = ingenic_ipu_get_priv_state(ipu, state);
0589     if (IS_ERR(ipu_state))
0590         return PTR_ERR(ipu_state);
0591 
0592     /* Request a full modeset if we are enabling or disabling the IPU. */
0593     if (!old_plane_state->crtc ^ !new_plane_state->crtc)
0594         crtc_state->mode_changed = true;
0595 
0596     if (!new_plane_state->crtc ||
0597         !crtc_state->mode.hdisplay || !crtc_state->mode.vdisplay)
0598         goto out_check_damage;
0599 
0600     /* Plane must be fully visible */
0601     if (new_plane_state->crtc_x < 0 || new_plane_state->crtc_y < 0 ||
0602         new_plane_state->crtc_x + new_plane_state->crtc_w > crtc_state->mode.hdisplay ||
0603         new_plane_state->crtc_y + new_plane_state->crtc_h > crtc_state->mode.vdisplay)
0604         return -EINVAL;
0605 
0606     /* Minimum size is 4x4 */
0607     if ((new_plane_state->src_w >> 16) < 4 || (new_plane_state->src_h >> 16) < 4)
0608         return -EINVAL;
0609 
0610     /* Input and output lines must have an even number of pixels. */
0611     if (((new_plane_state->src_w >> 16) & 1) || (new_plane_state->crtc_w & 1))
0612         return -EINVAL;
0613 
0614     if (!osd_changed(new_plane_state, old_plane_state))
0615         goto out_check_damage;
0616 
0617     crtc_state->mode_changed = true;
0618 
0619     xres = new_plane_state->src_w >> 16;
0620     yres = new_plane_state->src_h >> 16;
0621 
0622     /*
0623      * Increase the scaled image's theorical width/height until we find a
0624      * configuration that has valid scaling coefficients, up to 102% of the
0625      * screen's resolution. This makes sure that we can scale from almost
0626      * every resolution possible at the cost of a very small distorsion.
0627      * The CRTC_W / CRTC_H are not modified.
0628      */
0629     max_w = crtc_state->mode.hdisplay * 102 / 100;
0630     max_h = crtc_state->mode.vdisplay * 102 / 100;
0631 
0632     for (denom_w = xres, num_w = new_plane_state->crtc_w; num_w <= max_w; num_w++)
0633         if (!reduce_fraction(&num_w, &denom_w))
0634             break;
0635     if (num_w > max_w)
0636         return -EINVAL;
0637 
0638     for (denom_h = yres, num_h = new_plane_state->crtc_h; num_h <= max_h; num_h++)
0639         if (!reduce_fraction(&num_h, &denom_h))
0640             break;
0641     if (num_h > max_h)
0642         return -EINVAL;
0643 
0644     ipu_state->num_w = num_w;
0645     ipu_state->num_h = num_h;
0646     ipu_state->denom_w = denom_w;
0647     ipu_state->denom_h = denom_h;
0648 
0649 out_check_damage:
0650     if (ingenic_drm_map_noncoherent(ipu->master))
0651         drm_atomic_helper_check_plane_damage(state, new_plane_state);
0652 
0653     return 0;
0654 }
0655 
0656 static void ingenic_ipu_plane_atomic_disable(struct drm_plane *plane,
0657                          struct drm_atomic_state *state)
0658 {
0659     struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
0660 
0661     regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_STOP);
0662     regmap_clear_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CHIP_EN);
0663 
0664     ingenic_drm_plane_disable(ipu->master, plane);
0665 
0666     if (ipu->clk_enabled) {
0667         clk_disable(ipu->clk);
0668         ipu->clk_enabled = false;
0669     }
0670 }
0671 
0672 static const struct drm_plane_helper_funcs ingenic_ipu_plane_helper_funcs = {
0673     .atomic_update      = ingenic_ipu_plane_atomic_update,
0674     .atomic_check       = ingenic_ipu_plane_atomic_check,
0675     .atomic_disable     = ingenic_ipu_plane_atomic_disable,
0676 };
0677 
0678 static int
0679 ingenic_ipu_plane_atomic_get_property(struct drm_plane *plane,
0680                       const struct drm_plane_state *state,
0681                       struct drm_property *property, u64 *val)
0682 {
0683     struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
0684 
0685     if (property != ipu->sharpness_prop)
0686         return -EINVAL;
0687 
0688     *val = ipu->sharpness;
0689 
0690     return 0;
0691 }
0692 
0693 static int
0694 ingenic_ipu_plane_atomic_set_property(struct drm_plane *plane,
0695                       struct drm_plane_state *state,
0696                       struct drm_property *property, u64 val)
0697 {
0698     struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
0699     struct drm_crtc_state *crtc_state;
0700 
0701     if (property != ipu->sharpness_prop)
0702         return -EINVAL;
0703 
0704     ipu->sharpness = val;
0705 
0706     if (state->crtc) {
0707         crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc);
0708         if (WARN_ON(!crtc_state))
0709             return -EINVAL;
0710 
0711         crtc_state->mode_changed = true;
0712     }
0713 
0714     return 0;
0715 }
0716 
0717 static const struct drm_plane_funcs ingenic_ipu_plane_funcs = {
0718     .update_plane       = drm_atomic_helper_update_plane,
0719     .disable_plane      = drm_atomic_helper_disable_plane,
0720     .reset          = drm_atomic_helper_plane_reset,
0721     .destroy        = drm_plane_cleanup,
0722 
0723     .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
0724     .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
0725 
0726     .atomic_get_property    = ingenic_ipu_plane_atomic_get_property,
0727     .atomic_set_property    = ingenic_ipu_plane_atomic_set_property,
0728 };
0729 
0730 static struct drm_private_state *
0731 ingenic_ipu_duplicate_state(struct drm_private_obj *obj)
0732 {
0733     struct ingenic_ipu_private_state *state = to_ingenic_ipu_priv_state(obj->state);
0734 
0735     state = kmemdup(state, sizeof(*state), GFP_KERNEL);
0736     if (!state)
0737         return NULL;
0738 
0739     __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
0740 
0741     return &state->base;
0742 }
0743 
0744 static void ingenic_ipu_destroy_state(struct drm_private_obj *obj,
0745                       struct drm_private_state *state)
0746 {
0747     struct ingenic_ipu_private_state *priv_state = to_ingenic_ipu_priv_state(state);
0748 
0749     kfree(priv_state);
0750 }
0751 
0752 static const struct drm_private_state_funcs ingenic_ipu_private_state_funcs = {
0753     .atomic_duplicate_state = ingenic_ipu_duplicate_state,
0754     .atomic_destroy_state = ingenic_ipu_destroy_state,
0755 };
0756 
0757 static irqreturn_t ingenic_ipu_irq_handler(int irq, void *arg)
0758 {
0759     struct ingenic_ipu *ipu = arg;
0760     struct drm_crtc *crtc = drm_crtc_from_index(ipu->drm, 0);
0761     unsigned int dummy;
0762 
0763     /* dummy read allows CPU to reconfigure IPU */
0764     if (ipu->soc_info->manual_restart)
0765         regmap_read(ipu->map, JZ_REG_IPU_STATUS, &dummy);
0766 
0767     /* ACK interrupt */
0768     regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
0769 
0770     /* Set previously cached addresses */
0771     regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
0772     regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
0773     regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
0774 
0775     /* Run IPU for the new frame */
0776     if (ipu->soc_info->manual_restart)
0777         regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RUN);
0778 
0779     drm_crtc_handle_vblank(crtc);
0780 
0781     return IRQ_HANDLED;
0782 }
0783 
0784 static const struct regmap_config ingenic_ipu_regmap_config = {
0785     .reg_bits = 32,
0786     .val_bits = 32,
0787     .reg_stride = 4,
0788 
0789     .max_register = JZ_REG_IPU_OUT_PHY_T_ADDR,
0790 };
0791 
0792 static int ingenic_ipu_bind(struct device *dev, struct device *master, void *d)
0793 {
0794     struct platform_device *pdev = to_platform_device(dev);
0795     struct ingenic_ipu_private_state *private_state;
0796     const struct soc_info *soc_info;
0797     struct drm_device *drm = d;
0798     struct drm_plane *plane;
0799     struct ingenic_ipu *ipu;
0800     void __iomem *base;
0801     unsigned int sharpness_max;
0802     int err, irq;
0803 
0804     ipu = devm_kzalloc(dev, sizeof(*ipu), GFP_KERNEL);
0805     if (!ipu)
0806         return -ENOMEM;
0807 
0808     soc_info = of_device_get_match_data(dev);
0809     if (!soc_info) {
0810         dev_err(dev, "Missing platform data\n");
0811         return -EINVAL;
0812     }
0813 
0814     ipu->dev = dev;
0815     ipu->drm = drm;
0816     ipu->master = master;
0817     ipu->soc_info = soc_info;
0818 
0819     base = devm_platform_ioremap_resource(pdev, 0);
0820     if (IS_ERR(base)) {
0821         dev_err(dev, "Failed to get memory resource\n");
0822         return PTR_ERR(base);
0823     }
0824 
0825     ipu->map = devm_regmap_init_mmio(dev, base, &ingenic_ipu_regmap_config);
0826     if (IS_ERR(ipu->map)) {
0827         dev_err(dev, "Failed to create regmap\n");
0828         return PTR_ERR(ipu->map);
0829     }
0830 
0831     irq = platform_get_irq(pdev, 0);
0832     if (irq < 0)
0833         return irq;
0834 
0835     ipu->clk = devm_clk_get(dev, "ipu");
0836     if (IS_ERR(ipu->clk)) {
0837         dev_err(dev, "Failed to get pixel clock\n");
0838         return PTR_ERR(ipu->clk);
0839     }
0840 
0841     err = devm_request_irq(dev, irq, ingenic_ipu_irq_handler, 0,
0842                    dev_name(dev), ipu);
0843     if (err) {
0844         dev_err(dev, "Unable to request IRQ\n");
0845         return err;
0846     }
0847 
0848     plane = &ipu->plane;
0849     dev_set_drvdata(dev, plane);
0850 
0851     drm_plane_helper_add(plane, &ingenic_ipu_plane_helper_funcs);
0852 
0853     err = drm_universal_plane_init(drm, plane, 1, &ingenic_ipu_plane_funcs,
0854                        soc_info->formats, soc_info->num_formats,
0855                        NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
0856     if (err) {
0857         dev_err(dev, "Failed to init plane: %i\n", err);
0858         return err;
0859     }
0860 
0861     if (ingenic_drm_map_noncoherent(master))
0862         drm_plane_enable_fb_damage_clips(plane);
0863 
0864     /*
0865      * Sharpness settings range is [0,32]
0866      * 0       : nearest-neighbor
0867      * 1       : bilinear
0868      * 2 .. 32 : bicubic (translated to sharpness factor -0.25 .. -4.0)
0869      */
0870     sharpness_max = soc_info->has_bicubic ? 32 : 1;
0871     ipu->sharpness_prop = drm_property_create_range(drm, 0, "sharpness",
0872                             0, sharpness_max);
0873     if (!ipu->sharpness_prop) {
0874         dev_err(dev, "Unable to create sharpness property\n");
0875         return -ENOMEM;
0876     }
0877 
0878     /* Default sharpness factor: -0.125 * 8 = -1.0 */
0879     ipu->sharpness = soc_info->has_bicubic ? 8 : 1;
0880     drm_object_attach_property(&plane->base, ipu->sharpness_prop,
0881                    ipu->sharpness);
0882 
0883     err = clk_prepare(ipu->clk);
0884     if (err) {
0885         dev_err(dev, "Unable to prepare clock\n");
0886         return err;
0887     }
0888 
0889     private_state = kzalloc(sizeof(*private_state), GFP_KERNEL);
0890     if (!private_state) {
0891         err = -ENOMEM;
0892         goto err_clk_unprepare;
0893     }
0894 
0895     drm_atomic_private_obj_init(drm, &ipu->private_obj, &private_state->base,
0896                     &ingenic_ipu_private_state_funcs);
0897 
0898     return 0;
0899 
0900 err_clk_unprepare:
0901     clk_unprepare(ipu->clk);
0902     return err;
0903 }
0904 
0905 static void ingenic_ipu_unbind(struct device *dev,
0906                    struct device *master, void *d)
0907 {
0908     struct ingenic_ipu *ipu = dev_get_drvdata(dev);
0909 
0910     drm_atomic_private_obj_fini(&ipu->private_obj);
0911     clk_unprepare(ipu->clk);
0912 }
0913 
0914 static const struct component_ops ingenic_ipu_ops = {
0915     .bind = ingenic_ipu_bind,
0916     .unbind = ingenic_ipu_unbind,
0917 };
0918 
0919 static int ingenic_ipu_probe(struct platform_device *pdev)
0920 {
0921     return component_add(&pdev->dev, &ingenic_ipu_ops);
0922 }
0923 
0924 static int ingenic_ipu_remove(struct platform_device *pdev)
0925 {
0926     component_del(&pdev->dev, &ingenic_ipu_ops);
0927     return 0;
0928 }
0929 
0930 static const u32 jz4725b_ipu_formats[] = {
0931     /*
0932      * While officially supported, packed YUV 4:2:2 formats can cause
0933      * random hardware crashes on JZ4725B under certain circumstances.
0934      * It seems to happen with some specific resize ratios.
0935      * Until a proper workaround or fix is found, disable these formats.
0936     DRM_FORMAT_YUYV,
0937     DRM_FORMAT_YVYU,
0938     DRM_FORMAT_UYVY,
0939     DRM_FORMAT_VYUY,
0940     */
0941     DRM_FORMAT_YUV411,
0942     DRM_FORMAT_YUV420,
0943     DRM_FORMAT_YUV422,
0944     DRM_FORMAT_YUV444,
0945 };
0946 
0947 static const struct soc_info jz4725b_soc_info = {
0948     .formats    = jz4725b_ipu_formats,
0949     .num_formats    = ARRAY_SIZE(jz4725b_ipu_formats),
0950     .has_bicubic    = false,
0951     .manual_restart = true,
0952     .set_coefs  = jz4725b_set_coefs,
0953 };
0954 
0955 static const u32 jz4760_ipu_formats[] = {
0956     DRM_FORMAT_XRGB1555,
0957     DRM_FORMAT_XBGR1555,
0958     DRM_FORMAT_RGB565,
0959     DRM_FORMAT_BGR565,
0960     DRM_FORMAT_XRGB8888,
0961     DRM_FORMAT_XBGR8888,
0962     DRM_FORMAT_YUYV,
0963     DRM_FORMAT_YVYU,
0964     DRM_FORMAT_UYVY,
0965     DRM_FORMAT_VYUY,
0966     DRM_FORMAT_YUV411,
0967     DRM_FORMAT_YUV420,
0968     DRM_FORMAT_YUV422,
0969     DRM_FORMAT_YUV444,
0970     DRM_FORMAT_XYUV8888,
0971 };
0972 
0973 static const struct soc_info jz4760_soc_info = {
0974     .formats    = jz4760_ipu_formats,
0975     .num_formats    = ARRAY_SIZE(jz4760_ipu_formats),
0976     .has_bicubic    = true,
0977     .manual_restart = false,
0978     .set_coefs  = jz4760_set_coefs,
0979 };
0980 
0981 static const struct of_device_id ingenic_ipu_of_match[] = {
0982     { .compatible = "ingenic,jz4725b-ipu", .data = &jz4725b_soc_info },
0983     { .compatible = "ingenic,jz4760-ipu", .data = &jz4760_soc_info },
0984     { /* sentinel */ },
0985 };
0986 MODULE_DEVICE_TABLE(of, ingenic_ipu_of_match);
0987 
0988 static struct platform_driver ingenic_ipu_driver = {
0989     .driver = {
0990         .name = "ingenic-ipu",
0991         .of_match_table = ingenic_ipu_of_match,
0992     },
0993     .probe = ingenic_ipu_probe,
0994     .remove = ingenic_ipu_remove,
0995 };
0996 
0997 struct platform_driver *ingenic_ipu_driver_ptr = &ingenic_ipu_driver;
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