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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * i.MX IPUv3 DP Overlay Planes
0004  *
0005  * Copyright (C) 2013 Philipp Zabel, Pengutronix
0006  */
0007 
0008 #include <drm/drm_atomic.h>
0009 #include <drm/drm_atomic_helper.h>
0010 #include <drm/drm_blend.h>
0011 #include <drm/drm_fb_cma_helper.h>
0012 #include <drm/drm_fourcc.h>
0013 #include <drm/drm_framebuffer.h>
0014 #include <drm/drm_gem_atomic_helper.h>
0015 #include <drm/drm_gem_cma_helper.h>
0016 #include <drm/drm_managed.h>
0017 #include <drm/drm_plane_helper.h>
0018 
0019 #include <video/imx-ipu-v3.h>
0020 
0021 #include "imx-drm.h"
0022 #include "ipuv3-plane.h"
0023 
0024 struct ipu_plane_state {
0025     struct drm_plane_state base;
0026     bool use_pre;
0027 };
0028 
0029 static inline struct ipu_plane_state *
0030 to_ipu_plane_state(struct drm_plane_state *p)
0031 {
0032     return container_of(p, struct ipu_plane_state, base);
0033 }
0034 
0035 static unsigned int ipu_src_rect_width(const struct drm_plane_state *state)
0036 {
0037     return ALIGN(drm_rect_width(&state->src) >> 16, 8);
0038 }
0039 
0040 static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p)
0041 {
0042     return container_of(p, struct ipu_plane, base);
0043 }
0044 
0045 static const uint32_t ipu_plane_all_formats[] = {
0046     DRM_FORMAT_ARGB1555,
0047     DRM_FORMAT_XRGB1555,
0048     DRM_FORMAT_ABGR1555,
0049     DRM_FORMAT_XBGR1555,
0050     DRM_FORMAT_RGBA5551,
0051     DRM_FORMAT_BGRA5551,
0052     DRM_FORMAT_ARGB4444,
0053     DRM_FORMAT_ARGB8888,
0054     DRM_FORMAT_XRGB8888,
0055     DRM_FORMAT_ABGR8888,
0056     DRM_FORMAT_XBGR8888,
0057     DRM_FORMAT_RGBA8888,
0058     DRM_FORMAT_RGBX8888,
0059     DRM_FORMAT_BGRA8888,
0060     DRM_FORMAT_BGRX8888,
0061     DRM_FORMAT_UYVY,
0062     DRM_FORMAT_VYUY,
0063     DRM_FORMAT_YUYV,
0064     DRM_FORMAT_YVYU,
0065     DRM_FORMAT_YUV420,
0066     DRM_FORMAT_YVU420,
0067     DRM_FORMAT_YUV422,
0068     DRM_FORMAT_YVU422,
0069     DRM_FORMAT_YUV444,
0070     DRM_FORMAT_YVU444,
0071     DRM_FORMAT_NV12,
0072     DRM_FORMAT_NV16,
0073     DRM_FORMAT_RGB565,
0074     DRM_FORMAT_RGB565_A8,
0075     DRM_FORMAT_BGR565_A8,
0076     DRM_FORMAT_RGB888_A8,
0077     DRM_FORMAT_BGR888_A8,
0078     DRM_FORMAT_RGBX8888_A8,
0079     DRM_FORMAT_BGRX8888_A8,
0080 };
0081 
0082 static const uint32_t ipu_plane_rgb_formats[] = {
0083     DRM_FORMAT_ARGB1555,
0084     DRM_FORMAT_XRGB1555,
0085     DRM_FORMAT_ABGR1555,
0086     DRM_FORMAT_XBGR1555,
0087     DRM_FORMAT_RGBA5551,
0088     DRM_FORMAT_BGRA5551,
0089     DRM_FORMAT_ARGB4444,
0090     DRM_FORMAT_ARGB8888,
0091     DRM_FORMAT_XRGB8888,
0092     DRM_FORMAT_ABGR8888,
0093     DRM_FORMAT_XBGR8888,
0094     DRM_FORMAT_RGBA8888,
0095     DRM_FORMAT_RGBX8888,
0096     DRM_FORMAT_BGRA8888,
0097     DRM_FORMAT_BGRX8888,
0098     DRM_FORMAT_RGB565,
0099     DRM_FORMAT_RGB565_A8,
0100     DRM_FORMAT_BGR565_A8,
0101     DRM_FORMAT_RGB888_A8,
0102     DRM_FORMAT_BGR888_A8,
0103     DRM_FORMAT_RGBX8888_A8,
0104     DRM_FORMAT_BGRX8888_A8,
0105 };
0106 
0107 static const uint64_t ipu_format_modifiers[] = {
0108     DRM_FORMAT_MOD_LINEAR,
0109     DRM_FORMAT_MOD_INVALID
0110 };
0111 
0112 static const uint64_t pre_format_modifiers[] = {
0113     DRM_FORMAT_MOD_LINEAR,
0114     DRM_FORMAT_MOD_VIVANTE_TILED,
0115     DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
0116     DRM_FORMAT_MOD_INVALID
0117 };
0118 
0119 int ipu_plane_irq(struct ipu_plane *ipu_plane)
0120 {
0121     return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
0122                      IPU_IRQ_EOF);
0123 }
0124 
0125 static inline unsigned long
0126 drm_plane_state_to_eba(struct drm_plane_state *state, int plane)
0127 {
0128     struct drm_framebuffer *fb = state->fb;
0129     struct drm_gem_cma_object *cma_obj;
0130     int x = state->src.x1 >> 16;
0131     int y = state->src.y1 >> 16;
0132 
0133     cma_obj = drm_fb_cma_get_gem_obj(fb, plane);
0134     BUG_ON(!cma_obj);
0135 
0136     return cma_obj->paddr + fb->offsets[plane] + fb->pitches[plane] * y +
0137            fb->format->cpp[plane] * x;
0138 }
0139 
0140 static inline unsigned long
0141 drm_plane_state_to_ubo(struct drm_plane_state *state)
0142 {
0143     struct drm_framebuffer *fb = state->fb;
0144     struct drm_gem_cma_object *cma_obj;
0145     unsigned long eba = drm_plane_state_to_eba(state, 0);
0146     int x = state->src.x1 >> 16;
0147     int y = state->src.y1 >> 16;
0148 
0149     cma_obj = drm_fb_cma_get_gem_obj(fb, 1);
0150     BUG_ON(!cma_obj);
0151 
0152     x /= fb->format->hsub;
0153     y /= fb->format->vsub;
0154 
0155     return cma_obj->paddr + fb->offsets[1] + fb->pitches[1] * y +
0156            fb->format->cpp[1] * x - eba;
0157 }
0158 
0159 static inline unsigned long
0160 drm_plane_state_to_vbo(struct drm_plane_state *state)
0161 {
0162     struct drm_framebuffer *fb = state->fb;
0163     struct drm_gem_cma_object *cma_obj;
0164     unsigned long eba = drm_plane_state_to_eba(state, 0);
0165     int x = state->src.x1 >> 16;
0166     int y = state->src.y1 >> 16;
0167 
0168     cma_obj = drm_fb_cma_get_gem_obj(fb, 2);
0169     BUG_ON(!cma_obj);
0170 
0171     x /= fb->format->hsub;
0172     y /= fb->format->vsub;
0173 
0174     return cma_obj->paddr + fb->offsets[2] + fb->pitches[2] * y +
0175            fb->format->cpp[2] * x - eba;
0176 }
0177 
0178 static void ipu_plane_put_resources(struct drm_device *dev, void *ptr)
0179 {
0180     struct ipu_plane *ipu_plane = ptr;
0181 
0182     if (!IS_ERR_OR_NULL(ipu_plane->dp))
0183         ipu_dp_put(ipu_plane->dp);
0184     if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
0185         ipu_dmfc_put(ipu_plane->dmfc);
0186     if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
0187         ipu_idmac_put(ipu_plane->ipu_ch);
0188     if (!IS_ERR_OR_NULL(ipu_plane->alpha_ch))
0189         ipu_idmac_put(ipu_plane->alpha_ch);
0190 }
0191 
0192 static int ipu_plane_get_resources(struct drm_device *dev,
0193                    struct ipu_plane *ipu_plane)
0194 {
0195     int ret;
0196     int alpha_ch;
0197 
0198     ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
0199     if (IS_ERR(ipu_plane->ipu_ch)) {
0200         ret = PTR_ERR(ipu_plane->ipu_ch);
0201         DRM_ERROR("failed to get idmac channel: %d\n", ret);
0202         return ret;
0203     }
0204 
0205     ret = drmm_add_action_or_reset(dev, ipu_plane_put_resources, ipu_plane);
0206     if (ret)
0207         return ret;
0208 
0209     alpha_ch = ipu_channel_alpha_channel(ipu_plane->dma);
0210     if (alpha_ch >= 0) {
0211         ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch);
0212         if (IS_ERR(ipu_plane->alpha_ch)) {
0213             ret = PTR_ERR(ipu_plane->alpha_ch);
0214             DRM_ERROR("failed to get alpha idmac channel %d: %d\n",
0215                   alpha_ch, ret);
0216             return ret;
0217         }
0218     }
0219 
0220     ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
0221     if (IS_ERR(ipu_plane->dmfc)) {
0222         ret = PTR_ERR(ipu_plane->dmfc);
0223         DRM_ERROR("failed to get dmfc: ret %d\n", ret);
0224         return ret;
0225     }
0226 
0227     if (ipu_plane->dp_flow >= 0) {
0228         ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
0229         if (IS_ERR(ipu_plane->dp)) {
0230             ret = PTR_ERR(ipu_plane->dp);
0231             DRM_ERROR("failed to get dp flow: %d\n", ret);
0232             return ret;
0233         }
0234     }
0235 
0236     return 0;
0237 }
0238 
0239 static bool ipu_plane_separate_alpha(struct ipu_plane *ipu_plane)
0240 {
0241     switch (ipu_plane->base.state->fb->format->format) {
0242     case DRM_FORMAT_RGB565_A8:
0243     case DRM_FORMAT_BGR565_A8:
0244     case DRM_FORMAT_RGB888_A8:
0245     case DRM_FORMAT_BGR888_A8:
0246     case DRM_FORMAT_RGBX8888_A8:
0247     case DRM_FORMAT_BGRX8888_A8:
0248         return true;
0249     default:
0250         return false;
0251     }
0252 }
0253 
0254 static void ipu_plane_enable(struct ipu_plane *ipu_plane)
0255 {
0256     if (ipu_plane->dp)
0257         ipu_dp_enable(ipu_plane->ipu);
0258     ipu_dmfc_enable_channel(ipu_plane->dmfc);
0259     ipu_idmac_enable_channel(ipu_plane->ipu_ch);
0260     if (ipu_plane_separate_alpha(ipu_plane))
0261         ipu_idmac_enable_channel(ipu_plane->alpha_ch);
0262     if (ipu_plane->dp)
0263         ipu_dp_enable_channel(ipu_plane->dp);
0264 }
0265 
0266 void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel)
0267 {
0268     int ret;
0269 
0270     DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
0271 
0272     ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
0273     if (ret == -ETIMEDOUT) {
0274         DRM_ERROR("[PLANE:%d] IDMAC timeout\n",
0275               ipu_plane->base.base.id);
0276     }
0277 
0278     if (ipu_plane->dp && disable_dp_channel)
0279         ipu_dp_disable_channel(ipu_plane->dp, false);
0280     ipu_idmac_disable_channel(ipu_plane->ipu_ch);
0281     if (ipu_plane->alpha_ch)
0282         ipu_idmac_disable_channel(ipu_plane->alpha_ch);
0283     ipu_dmfc_disable_channel(ipu_plane->dmfc);
0284     if (ipu_plane->dp)
0285         ipu_dp_disable(ipu_plane->ipu);
0286     if (ipu_prg_present(ipu_plane->ipu))
0287         ipu_prg_channel_disable(ipu_plane->ipu_ch);
0288 }
0289 
0290 void ipu_plane_disable_deferred(struct drm_plane *plane)
0291 {
0292     struct ipu_plane *ipu_plane = to_ipu_plane(plane);
0293 
0294     if (ipu_plane->disabling) {
0295         ipu_plane->disabling = false;
0296         ipu_plane_disable(ipu_plane, false);
0297     }
0298 }
0299 
0300 static void ipu_plane_state_reset(struct drm_plane *plane)
0301 {
0302     struct ipu_plane_state *ipu_state;
0303 
0304     if (plane->state) {
0305         ipu_state = to_ipu_plane_state(plane->state);
0306         __drm_atomic_helper_plane_destroy_state(plane->state);
0307         kfree(ipu_state);
0308         plane->state = NULL;
0309     }
0310 
0311     ipu_state = kzalloc(sizeof(*ipu_state), GFP_KERNEL);
0312 
0313     if (ipu_state)
0314         __drm_atomic_helper_plane_reset(plane, &ipu_state->base);
0315 }
0316 
0317 static struct drm_plane_state *
0318 ipu_plane_duplicate_state(struct drm_plane *plane)
0319 {
0320     struct ipu_plane_state *state;
0321 
0322     if (WARN_ON(!plane->state))
0323         return NULL;
0324 
0325     state = kmalloc(sizeof(*state), GFP_KERNEL);
0326     if (state)
0327         __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
0328 
0329     return &state->base;
0330 }
0331 
0332 static void ipu_plane_destroy_state(struct drm_plane *plane,
0333                     struct drm_plane_state *state)
0334 {
0335     struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
0336 
0337     __drm_atomic_helper_plane_destroy_state(state);
0338     kfree(ipu_state);
0339 }
0340 
0341 static bool ipu_plane_format_mod_supported(struct drm_plane *plane,
0342                        uint32_t format, uint64_t modifier)
0343 {
0344     struct ipu_soc *ipu = to_ipu_plane(plane)->ipu;
0345 
0346     /* linear is supported for all planes and formats */
0347     if (modifier == DRM_FORMAT_MOD_LINEAR)
0348         return true;
0349 
0350     /*
0351      * Without a PRG the possible modifiers list only includes the linear
0352      * modifier, so we always take the early return from this function and
0353      * only end up here if the PRG is present.
0354      */
0355     return ipu_prg_format_supported(ipu, format, modifier);
0356 }
0357 
0358 static const struct drm_plane_funcs ipu_plane_funcs = {
0359     .update_plane   = drm_atomic_helper_update_plane,
0360     .disable_plane  = drm_atomic_helper_disable_plane,
0361     .reset      = ipu_plane_state_reset,
0362     .atomic_duplicate_state = ipu_plane_duplicate_state,
0363     .atomic_destroy_state   = ipu_plane_destroy_state,
0364     .format_mod_supported = ipu_plane_format_mod_supported,
0365 };
0366 
0367 static int ipu_plane_atomic_check(struct drm_plane *plane,
0368                   struct drm_atomic_state *state)
0369 {
0370     struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
0371                                        plane);
0372     struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
0373                                        plane);
0374     struct drm_crtc_state *crtc_state;
0375     struct device *dev = plane->dev->dev;
0376     struct drm_framebuffer *fb = new_state->fb;
0377     struct drm_framebuffer *old_fb = old_state->fb;
0378     unsigned long eba, ubo, vbo, old_ubo, old_vbo, alpha_eba;
0379     bool can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
0380     int ret;
0381 
0382     /* Ok to disable */
0383     if (!fb)
0384         return 0;
0385 
0386     if (WARN_ON(!new_state->crtc))
0387         return -EINVAL;
0388 
0389     crtc_state =
0390         drm_atomic_get_existing_crtc_state(state,
0391                            new_state->crtc);
0392     if (WARN_ON(!crtc_state))
0393         return -EINVAL;
0394 
0395     ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,
0396                           DRM_PLANE_HELPER_NO_SCALING,
0397                           DRM_PLANE_HELPER_NO_SCALING,
0398                           can_position, true);
0399     if (ret)
0400         return ret;
0401 
0402     /* nothing to check when disabling or disabled */
0403     if (!crtc_state->enable)
0404         return 0;
0405 
0406     switch (plane->type) {
0407     case DRM_PLANE_TYPE_PRIMARY:
0408         /* full plane minimum width is 13 pixels */
0409         if (drm_rect_width(&new_state->dst) < 13)
0410             return -EINVAL;
0411         break;
0412     case DRM_PLANE_TYPE_OVERLAY:
0413         break;
0414     default:
0415         dev_warn(dev, "Unsupported plane type %d\n", plane->type);
0416         return -EINVAL;
0417     }
0418 
0419     if (drm_rect_height(&new_state->dst) < 2)
0420         return -EINVAL;
0421 
0422     /*
0423      * We support resizing active plane or changing its format by
0424      * forcing CRTC mode change in plane's ->atomic_check callback
0425      * and disabling all affected active planes in CRTC's ->atomic_disable
0426      * callback.  The planes will be reenabled in plane's ->atomic_update
0427      * callback.
0428      */
0429     if (old_fb &&
0430         (drm_rect_width(&new_state->dst) != drm_rect_width(&old_state->dst) ||
0431          drm_rect_height(&new_state->dst) != drm_rect_height(&old_state->dst) ||
0432          fb->format != old_fb->format))
0433         crtc_state->mode_changed = true;
0434 
0435     eba = drm_plane_state_to_eba(new_state, 0);
0436 
0437     if (eba & 0x7)
0438         return -EINVAL;
0439 
0440     if (fb->pitches[0] < 1 || fb->pitches[0] > 16384)
0441         return -EINVAL;
0442 
0443     if (old_fb && fb->pitches[0] != old_fb->pitches[0])
0444         crtc_state->mode_changed = true;
0445 
0446     if (ALIGN(fb->width, 8) * fb->format->cpp[0] >
0447         fb->pitches[0] + fb->offsets[0]) {
0448         dev_warn(dev, "pitch is not big enough for 8 pixels alignment");
0449         return -EINVAL;
0450     }
0451 
0452     switch (fb->format->format) {
0453     case DRM_FORMAT_YUV420:
0454     case DRM_FORMAT_YVU420:
0455     case DRM_FORMAT_YUV422:
0456     case DRM_FORMAT_YVU422:
0457     case DRM_FORMAT_YUV444:
0458     case DRM_FORMAT_YVU444:
0459         /*
0460          * Multiplanar formats have to meet the following restrictions:
0461          * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
0462          * - EBA, UBO and VBO are a multiple of 8
0463          * - UBO and VBO are unsigned and not larger than 0xfffff8
0464          * - Only EBA may be changed while scanout is active
0465          * - The strides of U and V planes must be identical.
0466          */
0467         vbo = drm_plane_state_to_vbo(new_state);
0468 
0469         if (vbo & 0x7 || vbo > 0xfffff8)
0470             return -EINVAL;
0471 
0472         if (old_fb && (fb->format == old_fb->format)) {
0473             old_vbo = drm_plane_state_to_vbo(old_state);
0474             if (vbo != old_vbo)
0475                 crtc_state->mode_changed = true;
0476         }
0477 
0478         if (fb->pitches[1] != fb->pitches[2])
0479             return -EINVAL;
0480 
0481         fallthrough;
0482     case DRM_FORMAT_NV12:
0483     case DRM_FORMAT_NV16:
0484         ubo = drm_plane_state_to_ubo(new_state);
0485 
0486         if (ubo & 0x7 || ubo > 0xfffff8)
0487             return -EINVAL;
0488 
0489         if (old_fb && (fb->format == old_fb->format)) {
0490             old_ubo = drm_plane_state_to_ubo(old_state);
0491             if (ubo != old_ubo)
0492                 crtc_state->mode_changed = true;
0493         }
0494 
0495         if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
0496             return -EINVAL;
0497 
0498         if (old_fb && old_fb->pitches[1] != fb->pitches[1])
0499             crtc_state->mode_changed = true;
0500 
0501         /*
0502          * The x/y offsets must be even in case of horizontal/vertical
0503          * chroma subsampling.
0504          */
0505         if (((new_state->src.x1 >> 16) & (fb->format->hsub - 1)) ||
0506             ((new_state->src.y1 >> 16) & (fb->format->vsub - 1)))
0507             return -EINVAL;
0508         break;
0509     case DRM_FORMAT_RGB565_A8:
0510     case DRM_FORMAT_BGR565_A8:
0511     case DRM_FORMAT_RGB888_A8:
0512     case DRM_FORMAT_BGR888_A8:
0513     case DRM_FORMAT_RGBX8888_A8:
0514     case DRM_FORMAT_BGRX8888_A8:
0515         alpha_eba = drm_plane_state_to_eba(new_state, 1);
0516         if (alpha_eba & 0x7)
0517             return -EINVAL;
0518 
0519         if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
0520             return -EINVAL;
0521 
0522         if (old_fb && old_fb->pitches[1] != fb->pitches[1])
0523             crtc_state->mode_changed = true;
0524         break;
0525     }
0526 
0527     return 0;
0528 }
0529 
0530 static void ipu_plane_atomic_disable(struct drm_plane *plane,
0531                      struct drm_atomic_state *state)
0532 {
0533     struct ipu_plane *ipu_plane = to_ipu_plane(plane);
0534 
0535     if (ipu_plane->dp)
0536         ipu_dp_disable_channel(ipu_plane->dp, true);
0537     ipu_plane->disabling = true;
0538 }
0539 
0540 static int ipu_chan_assign_axi_id(int ipu_chan)
0541 {
0542     switch (ipu_chan) {
0543     case IPUV3_CHANNEL_MEM_BG_SYNC:
0544         return 1;
0545     case IPUV3_CHANNEL_MEM_FG_SYNC:
0546         return 2;
0547     case IPUV3_CHANNEL_MEM_DC_SYNC:
0548         return 3;
0549     default:
0550         return 0;
0551     }
0552 }
0553 
0554 static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride,
0555                  u8 *burstsize, u8 *num_bursts)
0556 {
0557     const unsigned int width_bytes = width * cpp;
0558     unsigned int npb, bursts;
0559 
0560     /* Maximum number of pixels per burst without overshooting stride */
0561     for (npb = 64 / cpp; npb > 0; --npb) {
0562         if (round_up(width_bytes, npb * cpp) <= stride)
0563             break;
0564     }
0565     *burstsize = npb;
0566 
0567     /* Maximum number of consecutive bursts without overshooting stride */
0568     for (bursts = 8; bursts > 1; bursts /= 2) {
0569         if (round_up(width_bytes, npb * cpp * bursts) <= stride)
0570             break;
0571     }
0572     *num_bursts = bursts;
0573 }
0574 
0575 static void ipu_plane_atomic_update(struct drm_plane *plane,
0576                     struct drm_atomic_state *state)
0577 {
0578     struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
0579                                        plane);
0580     struct ipu_plane *ipu_plane = to_ipu_plane(plane);
0581     struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
0582                                        plane);
0583     struct ipu_plane_state *ipu_state = to_ipu_plane_state(new_state);
0584     struct drm_crtc_state *crtc_state = new_state->crtc->state;
0585     struct drm_framebuffer *fb = new_state->fb;
0586     struct drm_rect *dst = &new_state->dst;
0587     unsigned long eba, ubo, vbo;
0588     unsigned long alpha_eba = 0;
0589     enum ipu_color_space ics;
0590     unsigned int axi_id = 0;
0591     const struct drm_format_info *info;
0592     u8 burstsize, num_bursts;
0593     u32 width, height;
0594     int active;
0595 
0596     if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG)
0597         ipu_dp_set_window_pos(ipu_plane->dp, dst->x1, dst->y1);
0598 
0599     switch (ipu_plane->dp_flow) {
0600     case IPU_DP_FLOW_SYNC_BG:
0601         if (new_state->normalized_zpos == 1) {
0602             ipu_dp_set_global_alpha(ipu_plane->dp,
0603                         !fb->format->has_alpha, 0xff,
0604                         true);
0605         } else {
0606             ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
0607         }
0608         break;
0609     case IPU_DP_FLOW_SYNC_FG:
0610         if (new_state->normalized_zpos == 1) {
0611             ipu_dp_set_global_alpha(ipu_plane->dp,
0612                         !fb->format->has_alpha, 0xff,
0613                         false);
0614         }
0615         break;
0616     }
0617 
0618     eba = drm_plane_state_to_eba(new_state, 0);
0619 
0620     /*
0621      * Configure PRG channel and attached PRE, this changes the EBA to an
0622      * internal SRAM location.
0623      */
0624     if (ipu_state->use_pre) {
0625         axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
0626         ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id,
0627                       ipu_src_rect_width(new_state),
0628                       drm_rect_height(&new_state->src) >> 16,
0629                       fb->pitches[0], fb->format->format,
0630                       fb->modifier, &eba);
0631     }
0632 
0633     if (!old_state->fb ||
0634         old_state->fb->format->format != fb->format->format ||
0635         old_state->color_encoding != new_state->color_encoding ||
0636         old_state->color_range != new_state->color_range) {
0637         ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
0638         switch (ipu_plane->dp_flow) {
0639         case IPU_DP_FLOW_SYNC_BG:
0640             ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
0641                          new_state->color_range, ics,
0642                          IPUV3_COLORSPACE_RGB);
0643             break;
0644         case IPU_DP_FLOW_SYNC_FG:
0645             ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
0646                          new_state->color_range, ics,
0647                          IPUV3_COLORSPACE_UNKNOWN);
0648             break;
0649         }
0650     }
0651 
0652     if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) {
0653         /* nothing to do if PRE is used */
0654         if (ipu_state->use_pre)
0655             return;
0656         active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
0657         ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
0658         ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
0659         if (ipu_plane_separate_alpha(ipu_plane)) {
0660             active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch);
0661             ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active,
0662                          alpha_eba);
0663             ipu_idmac_select_buffer(ipu_plane->alpha_ch, !active);
0664         }
0665         return;
0666     }
0667 
0668     ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
0669     switch (ipu_plane->dp_flow) {
0670     case IPU_DP_FLOW_SYNC_BG:
0671         ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
0672                      DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
0673                      IPUV3_COLORSPACE_RGB);
0674         break;
0675     case IPU_DP_FLOW_SYNC_FG:
0676         ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
0677                      DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
0678                      IPUV3_COLORSPACE_UNKNOWN);
0679         break;
0680     }
0681 
0682     ipu_dmfc_config_wait4eot(ipu_plane->dmfc, ALIGN(drm_rect_width(dst), 8));
0683 
0684     width = ipu_src_rect_width(new_state);
0685     height = drm_rect_height(&new_state->src) >> 16;
0686     info = drm_format_info(fb->format->format);
0687     ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
0688                  &burstsize, &num_bursts);
0689 
0690     ipu_cpmem_zero(ipu_plane->ipu_ch);
0691     ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height);
0692     ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
0693     ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
0694     ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
0695     ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
0696     ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
0697     ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
0698     ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
0699 
0700     switch (fb->format->format) {
0701     case DRM_FORMAT_YUV420:
0702     case DRM_FORMAT_YVU420:
0703     case DRM_FORMAT_YUV422:
0704     case DRM_FORMAT_YVU422:
0705     case DRM_FORMAT_YUV444:
0706     case DRM_FORMAT_YVU444:
0707         ubo = drm_plane_state_to_ubo(new_state);
0708         vbo = drm_plane_state_to_vbo(new_state);
0709         if (fb->format->format == DRM_FORMAT_YVU420 ||
0710             fb->format->format == DRM_FORMAT_YVU422 ||
0711             fb->format->format == DRM_FORMAT_YVU444)
0712             swap(ubo, vbo);
0713 
0714         ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
0715                           fb->pitches[1], ubo, vbo);
0716 
0717         dev_dbg(ipu_plane->base.dev->dev,
0718             "phy = %lu %lu %lu, x = %d, y = %d", eba, ubo, vbo,
0719             new_state->src.x1 >> 16, new_state->src.y1 >> 16);
0720         break;
0721     case DRM_FORMAT_NV12:
0722     case DRM_FORMAT_NV16:
0723         ubo = drm_plane_state_to_ubo(new_state);
0724 
0725         ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
0726                           fb->pitches[1], ubo, ubo);
0727 
0728         dev_dbg(ipu_plane->base.dev->dev,
0729             "phy = %lu %lu, x = %d, y = %d", eba, ubo,
0730             new_state->src.x1 >> 16, new_state->src.y1 >> 16);
0731         break;
0732     case DRM_FORMAT_RGB565_A8:
0733     case DRM_FORMAT_BGR565_A8:
0734     case DRM_FORMAT_RGB888_A8:
0735     case DRM_FORMAT_BGR888_A8:
0736     case DRM_FORMAT_RGBX8888_A8:
0737     case DRM_FORMAT_BGRX8888_A8:
0738         alpha_eba = drm_plane_state_to_eba(new_state, 1);
0739         num_bursts = 0;
0740 
0741         dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d",
0742             eba, alpha_eba, new_state->src.x1 >> 16,
0743             new_state->src.y1 >> 16);
0744 
0745         ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
0746 
0747         ipu_cpmem_zero(ipu_plane->alpha_ch);
0748         ipu_cpmem_set_resolution(ipu_plane->alpha_ch,
0749                      ipu_src_rect_width(new_state),
0750                      drm_rect_height(&new_state->src) >> 16);
0751         ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
0752         ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
0753         ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1);
0754         ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]);
0755         ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16);
0756         ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba);
0757         ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba);
0758         break;
0759     default:
0760         dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d",
0761             eba, new_state->src.x1 >> 16, new_state->src.y1 >> 16);
0762         break;
0763     }
0764     ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
0765     ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
0766     ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
0767     ipu_plane_enable(ipu_plane);
0768 }
0769 
0770 static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
0771     .atomic_check = ipu_plane_atomic_check,
0772     .atomic_disable = ipu_plane_atomic_disable,
0773     .atomic_update = ipu_plane_atomic_update,
0774 };
0775 
0776 bool ipu_plane_atomic_update_pending(struct drm_plane *plane)
0777 {
0778     struct ipu_plane *ipu_plane = to_ipu_plane(plane);
0779     struct drm_plane_state *state = plane->state;
0780     struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
0781 
0782     /* disabled crtcs must not block the update */
0783     if (!state->crtc)
0784         return false;
0785 
0786     if (ipu_state->use_pre)
0787         return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
0788 
0789     /*
0790      * Pretend no update is pending in the non-PRE/PRG case. For this to
0791      * happen, an atomic update would have to be deferred until after the
0792      * start of the next frame and simultaneously interrupt latency would
0793      * have to be high enough to let the atomic update finish and issue an
0794      * event before the previous end of frame interrupt handler can be
0795      * executed.
0796      */
0797     return false;
0798 }
0799 int ipu_planes_assign_pre(struct drm_device *dev,
0800               struct drm_atomic_state *state)
0801 {
0802     struct drm_crtc_state *old_crtc_state, *crtc_state;
0803     struct drm_plane_state *plane_state;
0804     struct ipu_plane_state *ipu_state;
0805     struct ipu_plane *ipu_plane;
0806     struct drm_plane *plane;
0807     struct drm_crtc *crtc;
0808     int available_pres = ipu_prg_max_active_channels();
0809     int ret, i;
0810 
0811     for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
0812         ret = drm_atomic_add_affected_planes(state, crtc);
0813         if (ret)
0814             return ret;
0815     }
0816 
0817     /*
0818      * We are going over the planes in 2 passes: first we assign PREs to
0819      * planes with a tiling modifier, which need the PREs to resolve into
0820      * linear. Any failure to assign a PRE there is fatal. In the second
0821      * pass we try to assign PREs to linear FBs, to improve memory access
0822      * patterns for them. Failure at this point is non-fatal, as we can
0823      * scan out linear FBs without a PRE.
0824      */
0825     for_each_new_plane_in_state(state, plane, plane_state, i) {
0826         ipu_state = to_ipu_plane_state(plane_state);
0827         ipu_plane = to_ipu_plane(plane);
0828 
0829         if (!plane_state->fb) {
0830             ipu_state->use_pre = false;
0831             continue;
0832         }
0833 
0834         if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||
0835             plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)
0836             continue;
0837 
0838         if (!ipu_prg_present(ipu_plane->ipu) || !available_pres)
0839             return -EINVAL;
0840 
0841         if (!ipu_prg_format_supported(ipu_plane->ipu,
0842                           plane_state->fb->format->format,
0843                           plane_state->fb->modifier))
0844             return -EINVAL;
0845 
0846         ipu_state->use_pre = true;
0847         available_pres--;
0848     }
0849 
0850     for_each_new_plane_in_state(state, plane, plane_state, i) {
0851         ipu_state = to_ipu_plane_state(plane_state);
0852         ipu_plane = to_ipu_plane(plane);
0853 
0854         if (!plane_state->fb) {
0855             ipu_state->use_pre = false;
0856             continue;
0857         }
0858 
0859         if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&
0860             plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)
0861             continue;
0862 
0863         /* make sure that modifier is initialized */
0864         plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;
0865 
0866         if (ipu_prg_present(ipu_plane->ipu) && available_pres &&
0867             ipu_prg_format_supported(ipu_plane->ipu,
0868                          plane_state->fb->format->format,
0869                          plane_state->fb->modifier)) {
0870             ipu_state->use_pre = true;
0871             available_pres--;
0872         } else {
0873             ipu_state->use_pre = false;
0874         }
0875     }
0876 
0877     return 0;
0878 }
0879 
0880 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
0881                  int dma, int dp, unsigned int possible_crtcs,
0882                  enum drm_plane_type type)
0883 {
0884     struct ipu_plane *ipu_plane;
0885     const uint64_t *modifiers = ipu_format_modifiers;
0886     unsigned int zpos = (type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
0887     unsigned int format_count;
0888     const uint32_t *formats;
0889     int ret;
0890 
0891     DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
0892               dma, dp, possible_crtcs);
0893 
0894     if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG) {
0895         formats = ipu_plane_all_formats;
0896         format_count = ARRAY_SIZE(ipu_plane_all_formats);
0897     } else {
0898         formats = ipu_plane_rgb_formats;
0899         format_count = ARRAY_SIZE(ipu_plane_rgb_formats);
0900     }
0901 
0902     if (ipu_prg_present(ipu))
0903         modifiers = pre_format_modifiers;
0904 
0905     ipu_plane = drmm_universal_plane_alloc(dev, struct ipu_plane, base,
0906                            possible_crtcs, &ipu_plane_funcs,
0907                            formats, format_count, modifiers,
0908                            type, NULL);
0909     if (IS_ERR(ipu_plane)) {
0910         DRM_ERROR("failed to allocate and initialize %s plane\n",
0911               zpos ? "overlay" : "primary");
0912         return ipu_plane;
0913     }
0914 
0915     ipu_plane->ipu = ipu;
0916     ipu_plane->dma = dma;
0917     ipu_plane->dp_flow = dp;
0918 
0919     drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs);
0920 
0921     if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG)
0922         ret = drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0,
0923                              1);
0924     else
0925         ret = drm_plane_create_zpos_immutable_property(&ipu_plane->base,
0926                                    0);
0927     if (ret)
0928         return ERR_PTR(ret);
0929 
0930     ret = drm_plane_create_color_properties(&ipu_plane->base,
0931             BIT(DRM_COLOR_YCBCR_BT601) |
0932             BIT(DRM_COLOR_YCBCR_BT709),
0933             BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
0934             DRM_COLOR_YCBCR_BT601,
0935             DRM_COLOR_YCBCR_LIMITED_RANGE);
0936     if (ret)
0937         return ERR_PTR(ret);
0938 
0939     ret = ipu_plane_get_resources(dev, ipu_plane);
0940     if (ret) {
0941         DRM_ERROR("failed to get %s plane resources: %pe\n",
0942               zpos ? "overlay" : "primary", &ret);
0943         return ERR_PTR(ret);
0944     }
0945 
0946     return ipu_plane;
0947 }
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