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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * i.MX drm driver - Television Encoder (TVEv2)
0004  *
0005  * Copyright (C) 2013 Philipp Zabel, Pengutronix
0006  */
0007 
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk.h>
0010 #include <linux/component.h>
0011 #include <linux/i2c.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015 #include <linux/regulator/consumer.h>
0016 #include <linux/videodev2.h>
0017 
0018 #include <video/imx-ipu-v3.h>
0019 
0020 #include <drm/drm_atomic_helper.h>
0021 #include <drm/drm_edid.h>
0022 #include <drm/drm_fb_helper.h>
0023 #include <drm/drm_managed.h>
0024 #include <drm/drm_probe_helper.h>
0025 #include <drm/drm_simple_kms_helper.h>
0026 
0027 #include "imx-drm.h"
0028 
0029 #define TVE_COM_CONF_REG    0x00
0030 #define TVE_TVDAC0_CONT_REG 0x28
0031 #define TVE_TVDAC1_CONT_REG 0x2c
0032 #define TVE_TVDAC2_CONT_REG 0x30
0033 #define TVE_CD_CONT_REG     0x34
0034 #define TVE_INT_CONT_REG    0x64
0035 #define TVE_STAT_REG        0x68
0036 #define TVE_TST_MODE_REG    0x6c
0037 #define TVE_MV_CONT_REG     0xdc
0038 
0039 /* TVE_COM_CONF_REG */
0040 #define TVE_SYNC_CH_2_EN    BIT(22)
0041 #define TVE_SYNC_CH_1_EN    BIT(21)
0042 #define TVE_SYNC_CH_0_EN    BIT(20)
0043 #define TVE_TV_OUT_MODE_MASK    (0x7 << 12)
0044 #define TVE_TV_OUT_DISABLE  (0x0 << 12)
0045 #define TVE_TV_OUT_CVBS_0   (0x1 << 12)
0046 #define TVE_TV_OUT_CVBS_2   (0x2 << 12)
0047 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
0048 #define TVE_TV_OUT_SVIDEO_0_1   (0x4 << 12)
0049 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2   (0x5 << 12)
0050 #define TVE_TV_OUT_YPBPR    (0x6 << 12)
0051 #define TVE_TV_OUT_RGB      (0x7 << 12)
0052 #define TVE_TV_STAND_MASK   (0xf << 8)
0053 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
0054 #define TVE_P2I_CONV_EN     BIT(7)
0055 #define TVE_INP_VIDEO_FORM  BIT(6)
0056 #define TVE_INP_YCBCR_422   (0x0 << 6)
0057 #define TVE_INP_YCBCR_444   (0x1 << 6)
0058 #define TVE_DATA_SOURCE_MASK    (0x3 << 4)
0059 #define TVE_DATA_SOURCE_BUS1    (0x0 << 4)
0060 #define TVE_DATA_SOURCE_BUS2    (0x1 << 4)
0061 #define TVE_DATA_SOURCE_EXT (0x2 << 4)
0062 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
0063 #define TVE_IPU_CLK_EN_OFS  3
0064 #define TVE_IPU_CLK_EN      BIT(3)
0065 #define TVE_DAC_SAMP_RATE_OFS   1
0066 #define TVE_DAC_SAMP_RATE_WIDTH 2
0067 #define TVE_DAC_SAMP_RATE_MASK  (0x3 << 1)
0068 #define TVE_DAC_FULL_RATE   (0x0 << 1)
0069 #define TVE_DAC_DIV2_RATE   (0x1 << 1)
0070 #define TVE_DAC_DIV4_RATE   (0x2 << 1)
0071 #define TVE_EN          BIT(0)
0072 
0073 /* TVE_TVDACx_CONT_REG */
0074 #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
0075 
0076 /* TVE_CD_CONT_REG */
0077 #define TVE_CD_CH_2_SM_EN   BIT(22)
0078 #define TVE_CD_CH_1_SM_EN   BIT(21)
0079 #define TVE_CD_CH_0_SM_EN   BIT(20)
0080 #define TVE_CD_CH_2_LM_EN   BIT(18)
0081 #define TVE_CD_CH_1_LM_EN   BIT(17)
0082 #define TVE_CD_CH_0_LM_EN   BIT(16)
0083 #define TVE_CD_CH_2_REF_LVL BIT(10)
0084 #define TVE_CD_CH_1_REF_LVL BIT(9)
0085 #define TVE_CD_CH_0_REF_LVL BIT(8)
0086 #define TVE_CD_EN       BIT(0)
0087 
0088 /* TVE_INT_CONT_REG */
0089 #define TVE_FRAME_END_IEN   BIT(13)
0090 #define TVE_CD_MON_END_IEN  BIT(2)
0091 #define TVE_CD_SM_IEN       BIT(1)
0092 #define TVE_CD_LM_IEN       BIT(0)
0093 
0094 /* TVE_TST_MODE_REG */
0095 #define TVE_TVDAC_TEST_MODE_MASK    (0x7 << 0)
0096 
0097 #define IMX_TVE_DAC_VOLTAGE 2750000
0098 
0099 enum {
0100     TVE_MODE_TVOUT,
0101     TVE_MODE_VGA,
0102 };
0103 
0104 struct imx_tve_encoder {
0105     struct drm_connector connector;
0106     struct drm_encoder encoder;
0107     struct imx_tve *tve;
0108 };
0109 
0110 struct imx_tve {
0111     struct device *dev;
0112     int mode;
0113     int di_hsync_pin;
0114     int di_vsync_pin;
0115 
0116     struct regmap *regmap;
0117     struct regulator *dac_reg;
0118     struct i2c_adapter *ddc;
0119     struct clk *clk;
0120     struct clk *di_sel_clk;
0121     struct clk_hw clk_hw_di;
0122     struct clk *di_clk;
0123 };
0124 
0125 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
0126 {
0127     return container_of(c, struct imx_tve_encoder, connector)->tve;
0128 }
0129 
0130 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
0131 {
0132     return container_of(e, struct imx_tve_encoder, encoder)->tve;
0133 }
0134 
0135 static void tve_enable(struct imx_tve *tve)
0136 {
0137     clk_prepare_enable(tve->clk);
0138     regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
0139 
0140     /* clear interrupt status register */
0141     regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
0142 
0143     /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
0144     if (tve->mode == TVE_MODE_VGA)
0145         regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
0146     else
0147         regmap_write(tve->regmap, TVE_INT_CONT_REG,
0148                  TVE_CD_SM_IEN |
0149                  TVE_CD_LM_IEN |
0150                  TVE_CD_MON_END_IEN);
0151 }
0152 
0153 static void tve_disable(struct imx_tve *tve)
0154 {
0155     regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
0156     clk_disable_unprepare(tve->clk);
0157 }
0158 
0159 static int tve_setup_tvout(struct imx_tve *tve)
0160 {
0161     return -ENOTSUPP;
0162 }
0163 
0164 static int tve_setup_vga(struct imx_tve *tve)
0165 {
0166     unsigned int mask;
0167     unsigned int val;
0168     int ret;
0169 
0170     /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
0171     ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
0172                  TVE_TVDAC_GAIN_MASK, 0x0a);
0173     if (ret)
0174         return ret;
0175 
0176     ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
0177                  TVE_TVDAC_GAIN_MASK, 0x0a);
0178     if (ret)
0179         return ret;
0180 
0181     ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
0182                  TVE_TVDAC_GAIN_MASK, 0x0a);
0183     if (ret)
0184         return ret;
0185 
0186     /* set configuration register */
0187     mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
0188     val  = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
0189     mask |= TVE_TV_STAND_MASK       | TVE_P2I_CONV_EN;
0190     val  |= TVE_TV_STAND_HD_1080P30 | 0;
0191     mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
0192     val  |= TVE_TV_OUT_RGB       | TVE_SYNC_CH_0_EN;
0193     ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
0194     if (ret)
0195         return ret;
0196 
0197     /* set test mode (as documented) */
0198     return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
0199                  TVE_TVDAC_TEST_MODE_MASK, 1);
0200 }
0201 
0202 static int imx_tve_connector_get_modes(struct drm_connector *connector)
0203 {
0204     struct imx_tve *tve = con_to_tve(connector);
0205     struct edid *edid;
0206     int ret = 0;
0207 
0208     if (!tve->ddc)
0209         return 0;
0210 
0211     edid = drm_get_edid(connector, tve->ddc);
0212     if (edid) {
0213         drm_connector_update_edid_property(connector, edid);
0214         ret = drm_add_edid_modes(connector, edid);
0215         kfree(edid);
0216     }
0217 
0218     return ret;
0219 }
0220 
0221 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
0222                     struct drm_display_mode *mode)
0223 {
0224     struct imx_tve *tve = con_to_tve(connector);
0225     unsigned long rate;
0226 
0227     /* pixel clock with 2x oversampling */
0228     rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
0229     if (rate == mode->clock)
0230         return MODE_OK;
0231 
0232     /* pixel clock without oversampling */
0233     rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
0234     if (rate == mode->clock)
0235         return MODE_OK;
0236 
0237     dev_warn(tve->dev, "ignoring mode %dx%d\n",
0238          mode->hdisplay, mode->vdisplay);
0239 
0240     return MODE_BAD;
0241 }
0242 
0243 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
0244                      struct drm_display_mode *orig_mode,
0245                      struct drm_display_mode *mode)
0246 {
0247     struct imx_tve *tve = enc_to_tve(encoder);
0248     unsigned long rounded_rate;
0249     unsigned long rate;
0250     int div = 1;
0251     int ret;
0252 
0253     /*
0254      * FIXME
0255      * we should try 4k * mode->clock first,
0256      * and enable 4x oversampling for lower resolutions
0257      */
0258     rate = 2000UL * mode->clock;
0259     clk_set_rate(tve->clk, rate);
0260     rounded_rate = clk_get_rate(tve->clk);
0261     if (rounded_rate >= rate)
0262         div = 2;
0263     clk_set_rate(tve->di_clk, rounded_rate / div);
0264 
0265     ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
0266     if (ret < 0) {
0267         dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
0268             ret);
0269     }
0270 
0271     regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
0272                TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
0273 
0274     if (tve->mode == TVE_MODE_VGA)
0275         ret = tve_setup_vga(tve);
0276     else
0277         ret = tve_setup_tvout(tve);
0278     if (ret)
0279         dev_err(tve->dev, "failed to set configuration: %d\n", ret);
0280 }
0281 
0282 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
0283 {
0284     struct imx_tve *tve = enc_to_tve(encoder);
0285 
0286     tve_enable(tve);
0287 }
0288 
0289 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
0290 {
0291     struct imx_tve *tve = enc_to_tve(encoder);
0292 
0293     tve_disable(tve);
0294 }
0295 
0296 static int imx_tve_atomic_check(struct drm_encoder *encoder,
0297                 struct drm_crtc_state *crtc_state,
0298                 struct drm_connector_state *conn_state)
0299 {
0300     struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
0301     struct imx_tve *tve = enc_to_tve(encoder);
0302 
0303     imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
0304     imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
0305     imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
0306 
0307     return 0;
0308 }
0309 
0310 static const struct drm_connector_funcs imx_tve_connector_funcs = {
0311     .fill_modes = drm_helper_probe_single_connector_modes,
0312     .destroy = imx_drm_connector_destroy,
0313     .reset = drm_atomic_helper_connector_reset,
0314     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
0315     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
0316 };
0317 
0318 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
0319     .get_modes = imx_tve_connector_get_modes,
0320     .mode_valid = imx_tve_connector_mode_valid,
0321 };
0322 
0323 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
0324     .mode_set = imx_tve_encoder_mode_set,
0325     .enable = imx_tve_encoder_enable,
0326     .disable = imx_tve_encoder_disable,
0327     .atomic_check = imx_tve_atomic_check,
0328 };
0329 
0330 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
0331 {
0332     struct imx_tve *tve = data;
0333     unsigned int val;
0334 
0335     regmap_read(tve->regmap, TVE_STAT_REG, &val);
0336 
0337     /* clear interrupt status register */
0338     regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
0339 
0340     return IRQ_HANDLED;
0341 }
0342 
0343 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
0344                         unsigned long parent_rate)
0345 {
0346     struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
0347     unsigned int val;
0348     int ret;
0349 
0350     ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
0351     if (ret < 0)
0352         return 0;
0353 
0354     switch (val & TVE_DAC_SAMP_RATE_MASK) {
0355     case TVE_DAC_DIV4_RATE:
0356         return parent_rate / 4;
0357     case TVE_DAC_DIV2_RATE:
0358         return parent_rate / 2;
0359     case TVE_DAC_FULL_RATE:
0360     default:
0361         return parent_rate;
0362     }
0363 
0364     return 0;
0365 }
0366 
0367 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
0368                   unsigned long *prate)
0369 {
0370     unsigned long div;
0371 
0372     div = *prate / rate;
0373     if (div >= 4)
0374         return *prate / 4;
0375     else if (div >= 2)
0376         return *prate / 2;
0377     return *prate;
0378 }
0379 
0380 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
0381                    unsigned long parent_rate)
0382 {
0383     struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
0384     unsigned long div;
0385     u32 val;
0386     int ret;
0387 
0388     div = parent_rate / rate;
0389     if (div >= 4)
0390         val = TVE_DAC_DIV4_RATE;
0391     else if (div >= 2)
0392         val = TVE_DAC_DIV2_RATE;
0393     else
0394         val = TVE_DAC_FULL_RATE;
0395 
0396     ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
0397                  TVE_DAC_SAMP_RATE_MASK, val);
0398 
0399     if (ret < 0) {
0400         dev_err(tve->dev, "failed to set divider: %d\n", ret);
0401         return ret;
0402     }
0403 
0404     return 0;
0405 }
0406 
0407 static const struct clk_ops clk_tve_di_ops = {
0408     .round_rate = clk_tve_di_round_rate,
0409     .set_rate = clk_tve_di_set_rate,
0410     .recalc_rate = clk_tve_di_recalc_rate,
0411 };
0412 
0413 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
0414 {
0415     const char *tve_di_parent[1];
0416     struct clk_init_data init = {
0417         .name = "tve_di",
0418         .ops = &clk_tve_di_ops,
0419         .num_parents = 1,
0420         .flags = 0,
0421     };
0422 
0423     tve_di_parent[0] = __clk_get_name(tve->clk);
0424     init.parent_names = (const char **)&tve_di_parent;
0425 
0426     tve->clk_hw_di.init = &init;
0427     tve->di_clk = devm_clk_register(tve->dev, &tve->clk_hw_di);
0428     if (IS_ERR(tve->di_clk)) {
0429         dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
0430             PTR_ERR(tve->di_clk));
0431         return PTR_ERR(tve->di_clk);
0432     }
0433 
0434     return 0;
0435 }
0436 
0437 static void imx_tve_disable_regulator(void *data)
0438 {
0439     struct imx_tve *tve = data;
0440 
0441     regulator_disable(tve->dac_reg);
0442 }
0443 
0444 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
0445 {
0446     return (reg % 4 == 0) && (reg <= 0xdc);
0447 }
0448 
0449 static struct regmap_config tve_regmap_config = {
0450     .reg_bits = 32,
0451     .val_bits = 32,
0452     .reg_stride = 4,
0453 
0454     .readable_reg = imx_tve_readable_reg,
0455 
0456     .fast_io = true,
0457 
0458     .max_register = 0xdc,
0459 };
0460 
0461 static const char * const imx_tve_modes[] = {
0462     [TVE_MODE_TVOUT]  = "tvout",
0463     [TVE_MODE_VGA] = "vga",
0464 };
0465 
0466 static int of_get_tve_mode(struct device_node *np)
0467 {
0468     const char *bm;
0469     int ret, i;
0470 
0471     ret = of_property_read_string(np, "fsl,tve-mode", &bm);
0472     if (ret < 0)
0473         return ret;
0474 
0475     for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
0476         if (!strcasecmp(bm, imx_tve_modes[i]))
0477             return i;
0478 
0479     return -EINVAL;
0480 }
0481 
0482 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
0483 {
0484     struct drm_device *drm = data;
0485     struct imx_tve *tve = dev_get_drvdata(dev);
0486     struct imx_tve_encoder *tvee;
0487     struct drm_encoder *encoder;
0488     struct drm_connector *connector;
0489     int encoder_type;
0490     int ret;
0491 
0492     encoder_type = tve->mode == TVE_MODE_VGA ?
0493                DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
0494 
0495     tvee = drmm_simple_encoder_alloc(drm, struct imx_tve_encoder, encoder,
0496                      encoder_type);
0497     if (IS_ERR(tvee))
0498         return PTR_ERR(tvee);
0499 
0500     tvee->tve = tve;
0501     encoder = &tvee->encoder;
0502     connector = &tvee->connector;
0503 
0504     ret = imx_drm_encoder_parse_of(drm, encoder, tve->dev->of_node);
0505     if (ret)
0506         return ret;
0507 
0508     drm_encoder_helper_add(encoder, &imx_tve_encoder_helper_funcs);
0509 
0510     drm_connector_helper_add(connector, &imx_tve_connector_helper_funcs);
0511     ret = drm_connector_init_with_ddc(drm, connector,
0512                       &imx_tve_connector_funcs,
0513                       DRM_MODE_CONNECTOR_VGA, tve->ddc);
0514     if (ret)
0515         return ret;
0516 
0517     return drm_connector_attach_encoder(connector, encoder);
0518 }
0519 
0520 static const struct component_ops imx_tve_ops = {
0521     .bind   = imx_tve_bind,
0522 };
0523 
0524 static int imx_tve_probe(struct platform_device *pdev)
0525 {
0526     struct device *dev = &pdev->dev;
0527     struct device_node *np = dev->of_node;
0528     struct device_node *ddc_node;
0529     struct imx_tve *tve;
0530     void __iomem *base;
0531     unsigned int val;
0532     int irq;
0533     int ret;
0534 
0535     tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
0536     if (!tve)
0537         return -ENOMEM;
0538 
0539     tve->dev = dev;
0540 
0541     ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
0542     if (ddc_node) {
0543         tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
0544         of_node_put(ddc_node);
0545     }
0546 
0547     tve->mode = of_get_tve_mode(np);
0548     if (tve->mode != TVE_MODE_VGA) {
0549         dev_err(dev, "only VGA mode supported, currently\n");
0550         return -EINVAL;
0551     }
0552 
0553     if (tve->mode == TVE_MODE_VGA) {
0554         ret = of_property_read_u32(np, "fsl,hsync-pin",
0555                        &tve->di_hsync_pin);
0556 
0557         if (ret < 0) {
0558             dev_err(dev, "failed to get hsync pin\n");
0559             return ret;
0560         }
0561 
0562         ret = of_property_read_u32(np, "fsl,vsync-pin",
0563                        &tve->di_vsync_pin);
0564 
0565         if (ret < 0) {
0566             dev_err(dev, "failed to get vsync pin\n");
0567             return ret;
0568         }
0569     }
0570 
0571     base = devm_platform_ioremap_resource(pdev, 0);
0572     if (IS_ERR(base))
0573         return PTR_ERR(base);
0574 
0575     tve_regmap_config.lock_arg = tve;
0576     tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
0577                         &tve_regmap_config);
0578     if (IS_ERR(tve->regmap)) {
0579         dev_err(dev, "failed to init regmap: %ld\n",
0580             PTR_ERR(tve->regmap));
0581         return PTR_ERR(tve->regmap);
0582     }
0583 
0584     irq = platform_get_irq(pdev, 0);
0585     if (irq < 0)
0586         return irq;
0587 
0588     ret = devm_request_threaded_irq(dev, irq, NULL,
0589                     imx_tve_irq_handler, IRQF_ONESHOT,
0590                     "imx-tve", tve);
0591     if (ret < 0) {
0592         dev_err(dev, "failed to request irq: %d\n", ret);
0593         return ret;
0594     }
0595 
0596     tve->dac_reg = devm_regulator_get(dev, "dac");
0597     if (!IS_ERR(tve->dac_reg)) {
0598         if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
0599             dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
0600         ret = regulator_enable(tve->dac_reg);
0601         if (ret)
0602             return ret;
0603         ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
0604         if (ret)
0605             return ret;
0606     }
0607 
0608     tve->clk = devm_clk_get(dev, "tve");
0609     if (IS_ERR(tve->clk)) {
0610         dev_err(dev, "failed to get high speed tve clock: %ld\n",
0611             PTR_ERR(tve->clk));
0612         return PTR_ERR(tve->clk);
0613     }
0614 
0615     /* this is the IPU DI clock input selector, can be parented to tve_di */
0616     tve->di_sel_clk = devm_clk_get(dev, "di_sel");
0617     if (IS_ERR(tve->di_sel_clk)) {
0618         dev_err(dev, "failed to get ipu di mux clock: %ld\n",
0619             PTR_ERR(tve->di_sel_clk));
0620         return PTR_ERR(tve->di_sel_clk);
0621     }
0622 
0623     ret = tve_clk_init(tve, base);
0624     if (ret < 0)
0625         return ret;
0626 
0627     ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
0628     if (ret < 0) {
0629         dev_err(dev, "failed to read configuration register: %d\n",
0630             ret);
0631         return ret;
0632     }
0633     if (val != 0x00100000) {
0634         dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
0635         return -ENODEV;
0636     }
0637 
0638     /* disable cable detection for VGA mode */
0639     ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
0640     if (ret)
0641         return ret;
0642 
0643     platform_set_drvdata(pdev, tve);
0644 
0645     return component_add(dev, &imx_tve_ops);
0646 }
0647 
0648 static int imx_tve_remove(struct platform_device *pdev)
0649 {
0650     component_del(&pdev->dev, &imx_tve_ops);
0651     return 0;
0652 }
0653 
0654 static const struct of_device_id imx_tve_dt_ids[] = {
0655     { .compatible = "fsl,imx53-tve", },
0656     { /* sentinel */ }
0657 };
0658 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
0659 
0660 static struct platform_driver imx_tve_driver = {
0661     .probe      = imx_tve_probe,
0662     .remove     = imx_tve_remove,
0663     .driver     = {
0664         .of_match_table = imx_tve_dt_ids,
0665         .name   = "imx-tve",
0666     },
0667 };
0668 
0669 module_platform_driver(imx_tve_driver);
0670 
0671 MODULE_DESCRIPTION("i.MX Television Encoder driver");
0672 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
0673 MODULE_LICENSE("GPL");
0674 MODULE_ALIAS("platform:imx-tve");
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