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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * i.MX drm driver - LVDS display bridge
0004  *
0005  * Copyright (C) 2012 Sascha Hauer, Pengutronix
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/component.h>
0010 #include <linux/media-bus-format.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/of_graph.h>
0016 #include <linux/regmap.h>
0017 #include <linux/videodev2.h>
0018 
0019 #include <video/of_display_timing.h>
0020 #include <video/of_videomode.h>
0021 
0022 #include <drm/drm_atomic.h>
0023 #include <drm/drm_atomic_helper.h>
0024 #include <drm/drm_bridge.h>
0025 #include <drm/drm_edid.h>
0026 #include <drm/drm_fb_helper.h>
0027 #include <drm/drm_managed.h>
0028 #include <drm/drm_of.h>
0029 #include <drm/drm_panel.h>
0030 #include <drm/drm_print.h>
0031 #include <drm/drm_probe_helper.h>
0032 #include <drm/drm_simple_kms_helper.h>
0033 
0034 #include "imx-drm.h"
0035 
0036 #define DRIVER_NAME "imx-ldb"
0037 
0038 #define LDB_CH0_MODE_EN_TO_DI0      (1 << 0)
0039 #define LDB_CH0_MODE_EN_TO_DI1      (3 << 0)
0040 #define LDB_CH0_MODE_EN_MASK        (3 << 0)
0041 #define LDB_CH1_MODE_EN_TO_DI0      (1 << 2)
0042 #define LDB_CH1_MODE_EN_TO_DI1      (3 << 2)
0043 #define LDB_CH1_MODE_EN_MASK        (3 << 2)
0044 #define LDB_SPLIT_MODE_EN       (1 << 4)
0045 #define LDB_DATA_WIDTH_CH0_24       (1 << 5)
0046 #define LDB_BIT_MAP_CH0_JEIDA       (1 << 6)
0047 #define LDB_DATA_WIDTH_CH1_24       (1 << 7)
0048 #define LDB_BIT_MAP_CH1_JEIDA       (1 << 8)
0049 #define LDB_DI0_VS_POL_ACT_LOW      (1 << 9)
0050 #define LDB_DI1_VS_POL_ACT_LOW      (1 << 10)
0051 #define LDB_BGREF_RMODE_INT     (1 << 15)
0052 
0053 struct imx_ldb_channel;
0054 
0055 struct imx_ldb_encoder {
0056     struct drm_connector connector;
0057     struct drm_encoder encoder;
0058     struct imx_ldb_channel *channel;
0059 };
0060 
0061 struct imx_ldb;
0062 
0063 struct imx_ldb_channel {
0064     struct imx_ldb *ldb;
0065 
0066     /* Defines what is connected to the ldb, only one at a time */
0067     struct drm_panel *panel;
0068     struct drm_bridge *bridge;
0069 
0070     struct device_node *child;
0071     struct i2c_adapter *ddc;
0072     int chno;
0073     void *edid;
0074     struct drm_display_mode mode;
0075     int mode_valid;
0076     u32 bus_format;
0077     u32 bus_flags;
0078 };
0079 
0080 static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
0081 {
0082     return container_of(c, struct imx_ldb_encoder, connector)->channel;
0083 }
0084 
0085 static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
0086 {
0087     return container_of(e, struct imx_ldb_encoder, encoder)->channel;
0088 }
0089 
0090 struct bus_mux {
0091     int reg;
0092     int shift;
0093     int mask;
0094 };
0095 
0096 struct imx_ldb {
0097     struct regmap *regmap;
0098     struct device *dev;
0099     struct imx_ldb_channel channel[2];
0100     struct clk *clk[2]; /* our own clock */
0101     struct clk *clk_sel[4]; /* parent of display clock */
0102     struct clk *clk_parent[4]; /* original parent of clk_sel */
0103     struct clk *clk_pll[2]; /* upstream clock we can adjust */
0104     u32 ldb_ctrl;
0105     const struct bus_mux *lvds_mux;
0106 };
0107 
0108 static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
0109                       u32 bus_format)
0110 {
0111     struct imx_ldb *ldb = imx_ldb_ch->ldb;
0112     int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
0113 
0114     switch (bus_format) {
0115     case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
0116         break;
0117     case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
0118         if (imx_ldb_ch->chno == 0 || dual)
0119             ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
0120         if (imx_ldb_ch->chno == 1 || dual)
0121             ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
0122         break;
0123     case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
0124         if (imx_ldb_ch->chno == 0 || dual)
0125             ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
0126                      LDB_BIT_MAP_CH0_JEIDA;
0127         if (imx_ldb_ch->chno == 1 || dual)
0128             ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
0129                      LDB_BIT_MAP_CH1_JEIDA;
0130         break;
0131     }
0132 }
0133 
0134 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
0135 {
0136     struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
0137     int num_modes;
0138 
0139     num_modes = drm_panel_get_modes(imx_ldb_ch->panel, connector);
0140     if (num_modes > 0)
0141         return num_modes;
0142 
0143     if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
0144         imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
0145 
0146     if (imx_ldb_ch->edid) {
0147         drm_connector_update_edid_property(connector,
0148                             imx_ldb_ch->edid);
0149         num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
0150     }
0151 
0152     if (imx_ldb_ch->mode_valid) {
0153         struct drm_display_mode *mode;
0154 
0155         mode = drm_mode_duplicate(connector->dev, &imx_ldb_ch->mode);
0156         if (!mode)
0157             return -EINVAL;
0158         mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
0159         drm_mode_probed_add(connector, mode);
0160         num_modes++;
0161     }
0162 
0163     return num_modes;
0164 }
0165 
0166 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
0167         unsigned long serial_clk, unsigned long di_clk)
0168 {
0169     int ret;
0170 
0171     dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
0172             clk_get_rate(ldb->clk_pll[chno]), serial_clk);
0173     clk_set_rate(ldb->clk_pll[chno], serial_clk);
0174 
0175     dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
0176             clk_get_rate(ldb->clk_pll[chno]));
0177 
0178     dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
0179             clk_get_rate(ldb->clk[chno]),
0180             (long int)di_clk);
0181     clk_set_rate(ldb->clk[chno], di_clk);
0182 
0183     dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
0184             clk_get_rate(ldb->clk[chno]));
0185 
0186     /* set display clock mux to LDB input clock */
0187     ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
0188     if (ret)
0189         dev_err(ldb->dev,
0190             "unable to set di%d parent clock to ldb_di%d\n", mux,
0191             chno);
0192 }
0193 
0194 static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
0195 {
0196     struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
0197     struct imx_ldb *ldb = imx_ldb_ch->ldb;
0198     int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
0199     int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
0200 
0201     if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
0202         dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
0203         return;
0204     }
0205 
0206     drm_panel_prepare(imx_ldb_ch->panel);
0207 
0208     if (dual) {
0209         clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
0210         clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
0211 
0212         clk_prepare_enable(ldb->clk[0]);
0213         clk_prepare_enable(ldb->clk[1]);
0214     } else {
0215         clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
0216     }
0217 
0218     if (imx_ldb_ch == &ldb->channel[0] || dual) {
0219         ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
0220         if (mux == 0 || ldb->lvds_mux)
0221             ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
0222         else if (mux == 1)
0223             ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
0224     }
0225     if (imx_ldb_ch == &ldb->channel[1] || dual) {
0226         ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
0227         if (mux == 1 || ldb->lvds_mux)
0228             ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
0229         else if (mux == 0)
0230             ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
0231     }
0232 
0233     if (ldb->lvds_mux) {
0234         const struct bus_mux *lvds_mux = NULL;
0235 
0236         if (imx_ldb_ch == &ldb->channel[0])
0237             lvds_mux = &ldb->lvds_mux[0];
0238         else if (imx_ldb_ch == &ldb->channel[1])
0239             lvds_mux = &ldb->lvds_mux[1];
0240 
0241         regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
0242                    mux << lvds_mux->shift);
0243     }
0244 
0245     regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
0246 
0247     drm_panel_enable(imx_ldb_ch->panel);
0248 }
0249 
0250 static void
0251 imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
0252                 struct drm_crtc_state *crtc_state,
0253                 struct drm_connector_state *connector_state)
0254 {
0255     struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
0256     struct drm_display_mode *mode = &crtc_state->adjusted_mode;
0257     struct imx_ldb *ldb = imx_ldb_ch->ldb;
0258     int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
0259     unsigned long serial_clk;
0260     unsigned long di_clk = mode->clock * 1000;
0261     int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
0262     u32 bus_format = imx_ldb_ch->bus_format;
0263 
0264     if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
0265         dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
0266         return;
0267     }
0268 
0269     if (mode->clock > 170000) {
0270         dev_warn(ldb->dev,
0271              "%s: mode exceeds 170 MHz pixel clock\n", __func__);
0272     }
0273     if (mode->clock > 85000 && !dual) {
0274         dev_warn(ldb->dev,
0275              "%s: mode exceeds 85 MHz pixel clock\n", __func__);
0276     }
0277 
0278     if (!IS_ALIGNED(mode->hdisplay, 8)) {
0279         dev_warn(ldb->dev,
0280              "%s: hdisplay does not align to 8 byte\n", __func__);
0281     }
0282 
0283     if (dual) {
0284         serial_clk = 3500UL * mode->clock;
0285         imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
0286         imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
0287     } else {
0288         serial_clk = 7000UL * mode->clock;
0289         imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
0290                   di_clk);
0291     }
0292 
0293     /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
0294     if (imx_ldb_ch == &ldb->channel[0] || dual) {
0295         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
0296             ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
0297         else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
0298             ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
0299     }
0300     if (imx_ldb_ch == &ldb->channel[1] || dual) {
0301         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
0302             ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
0303         else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
0304             ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
0305     }
0306 
0307     if (!bus_format) {
0308         struct drm_connector *connector = connector_state->connector;
0309         struct drm_display_info *di = &connector->display_info;
0310 
0311         if (di->num_bus_formats)
0312             bus_format = di->bus_formats[0];
0313     }
0314     imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
0315 }
0316 
0317 static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
0318 {
0319     struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
0320     struct imx_ldb *ldb = imx_ldb_ch->ldb;
0321     int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
0322     int mux, ret;
0323 
0324     drm_panel_disable(imx_ldb_ch->panel);
0325 
0326     if (imx_ldb_ch == &ldb->channel[0] || dual)
0327         ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
0328     if (imx_ldb_ch == &ldb->channel[1] || dual)
0329         ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
0330 
0331     regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
0332 
0333     if (dual) {
0334         clk_disable_unprepare(ldb->clk[0]);
0335         clk_disable_unprepare(ldb->clk[1]);
0336     }
0337 
0338     if (ldb->lvds_mux) {
0339         const struct bus_mux *lvds_mux = NULL;
0340 
0341         if (imx_ldb_ch == &ldb->channel[0])
0342             lvds_mux = &ldb->lvds_mux[0];
0343         else if (imx_ldb_ch == &ldb->channel[1])
0344             lvds_mux = &ldb->lvds_mux[1];
0345 
0346         regmap_read(ldb->regmap, lvds_mux->reg, &mux);
0347         mux &= lvds_mux->mask;
0348         mux >>= lvds_mux->shift;
0349     } else {
0350         mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
0351     }
0352 
0353     /* set display clock mux back to original input clock */
0354     ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
0355     if (ret)
0356         dev_err(ldb->dev,
0357             "unable to set di%d parent clock to original parent\n",
0358             mux);
0359 
0360     drm_panel_unprepare(imx_ldb_ch->panel);
0361 }
0362 
0363 static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
0364                     struct drm_crtc_state *crtc_state,
0365                     struct drm_connector_state *conn_state)
0366 {
0367     struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
0368     struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
0369     struct drm_display_info *di = &conn_state->connector->display_info;
0370     u32 bus_format = imx_ldb_ch->bus_format;
0371 
0372     /* Bus format description in DT overrides connector display info. */
0373     if (!bus_format && di->num_bus_formats) {
0374         bus_format = di->bus_formats[0];
0375         imx_crtc_state->bus_flags = di->bus_flags;
0376     } else {
0377         bus_format = imx_ldb_ch->bus_format;
0378         imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
0379     }
0380     switch (bus_format) {
0381     case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
0382         imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
0383         break;
0384     case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
0385     case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
0386         imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
0387         break;
0388     default:
0389         return -EINVAL;
0390     }
0391 
0392     imx_crtc_state->di_hsync_pin = 2;
0393     imx_crtc_state->di_vsync_pin = 3;
0394 
0395     return 0;
0396 }
0397 
0398 
0399 static const struct drm_connector_funcs imx_ldb_connector_funcs = {
0400     .fill_modes = drm_helper_probe_single_connector_modes,
0401     .destroy = imx_drm_connector_destroy,
0402     .reset = drm_atomic_helper_connector_reset,
0403     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
0404     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
0405 };
0406 
0407 static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
0408     .get_modes = imx_ldb_connector_get_modes,
0409 };
0410 
0411 static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
0412     .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
0413     .enable = imx_ldb_encoder_enable,
0414     .disable = imx_ldb_encoder_disable,
0415     .atomic_check = imx_ldb_encoder_atomic_check,
0416 };
0417 
0418 static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
0419 {
0420     char clkname[16];
0421 
0422     snprintf(clkname, sizeof(clkname), "di%d", chno);
0423     ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
0424     if (IS_ERR(ldb->clk[chno]))
0425         return PTR_ERR(ldb->clk[chno]);
0426 
0427     snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
0428     ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
0429 
0430     return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
0431 }
0432 
0433 static int imx_ldb_register(struct drm_device *drm,
0434     struct imx_ldb_channel *imx_ldb_ch)
0435 {
0436     struct imx_ldb *ldb = imx_ldb_ch->ldb;
0437     struct imx_ldb_encoder *ldb_encoder;
0438     struct drm_connector *connector;
0439     struct drm_encoder *encoder;
0440     int ret;
0441 
0442     ldb_encoder = drmm_simple_encoder_alloc(drm, struct imx_ldb_encoder,
0443                         encoder, DRM_MODE_ENCODER_LVDS);
0444     if (IS_ERR(ldb_encoder))
0445         return PTR_ERR(ldb_encoder);
0446 
0447     ldb_encoder->channel = imx_ldb_ch;
0448     connector = &ldb_encoder->connector;
0449     encoder = &ldb_encoder->encoder;
0450 
0451     ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
0452     if (ret)
0453         return ret;
0454 
0455     ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
0456     if (ret)
0457         return ret;
0458 
0459     if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
0460         ret = imx_ldb_get_clk(ldb, 1);
0461         if (ret)
0462             return ret;
0463     }
0464 
0465     drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
0466 
0467     if (imx_ldb_ch->bridge) {
0468         ret = drm_bridge_attach(encoder, imx_ldb_ch->bridge, NULL, 0);
0469         if (ret)
0470             return ret;
0471     } else {
0472         /*
0473          * We want to add the connector whenever there is no bridge
0474          * that brings its own, not only when there is a panel. For
0475          * historical reasons, the ldb driver can also work without
0476          * a panel.
0477          */
0478         drm_connector_helper_add(connector,
0479                      &imx_ldb_connector_helper_funcs);
0480         drm_connector_init_with_ddc(drm, connector,
0481                         &imx_ldb_connector_funcs,
0482                         DRM_MODE_CONNECTOR_LVDS,
0483                         imx_ldb_ch->ddc);
0484         drm_connector_attach_encoder(connector, encoder);
0485     }
0486 
0487     return 0;
0488 }
0489 
0490 struct imx_ldb_bit_mapping {
0491     u32 bus_format;
0492     u32 datawidth;
0493     const char * const mapping;
0494 };
0495 
0496 static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
0497     { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,  18, "spwg" },
0498     { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,  24, "spwg" },
0499     { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
0500 };
0501 
0502 static u32 of_get_bus_format(struct device *dev, struct device_node *np)
0503 {
0504     const char *bm;
0505     u32 datawidth = 0;
0506     int ret, i;
0507 
0508     ret = of_property_read_string(np, "fsl,data-mapping", &bm);
0509     if (ret < 0)
0510         return ret;
0511 
0512     of_property_read_u32(np, "fsl,data-width", &datawidth);
0513 
0514     for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
0515         if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
0516             datawidth == imx_ldb_bit_mappings[i].datawidth)
0517             return imx_ldb_bit_mappings[i].bus_format;
0518     }
0519 
0520     dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
0521 
0522     return -ENOENT;
0523 }
0524 
0525 static struct bus_mux imx6q_lvds_mux[2] = {
0526     {
0527         .reg = IOMUXC_GPR3,
0528         .shift = 6,
0529         .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
0530     }, {
0531         .reg = IOMUXC_GPR3,
0532         .shift = 8,
0533         .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
0534     }
0535 };
0536 
0537 /*
0538  * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
0539  * of_match_device will walk through this list and take the first entry
0540  * matching any of its compatible values. Therefore, the more generic
0541  * entries (in this case fsl,imx53-ldb) need to be ordered last.
0542  */
0543 static const struct of_device_id imx_ldb_dt_ids[] = {
0544     { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
0545     { .compatible = "fsl,imx53-ldb", .data = NULL, },
0546     { }
0547 };
0548 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
0549 
0550 static int imx_ldb_panel_ddc(struct device *dev,
0551         struct imx_ldb_channel *channel, struct device_node *child)
0552 {
0553     struct device_node *ddc_node;
0554     const u8 *edidp;
0555     int ret;
0556 
0557     ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
0558     if (ddc_node) {
0559         channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
0560         of_node_put(ddc_node);
0561         if (!channel->ddc) {
0562             dev_warn(dev, "failed to get ddc i2c adapter\n");
0563             return -EPROBE_DEFER;
0564         }
0565     }
0566 
0567     if (!channel->ddc) {
0568         int edid_len;
0569 
0570         /* if no DDC available, fallback to hardcoded EDID */
0571         dev_dbg(dev, "no ddc available\n");
0572 
0573         edidp = of_get_property(child, "edid", &edid_len);
0574         if (edidp) {
0575             channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
0576             if (!channel->edid)
0577                 return -ENOMEM;
0578         } else if (!channel->panel) {
0579             /* fallback to display-timings node */
0580             ret = of_get_drm_display_mode(child,
0581                               &channel->mode,
0582                               &channel->bus_flags,
0583                               OF_USE_NATIVE_MODE);
0584             if (!ret)
0585                 channel->mode_valid = 1;
0586         }
0587     }
0588     return 0;
0589 }
0590 
0591 static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
0592 {
0593     struct drm_device *drm = data;
0594     struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
0595     int ret;
0596     int i;
0597 
0598     for (i = 0; i < 2; i++) {
0599         struct imx_ldb_channel *channel = &imx_ldb->channel[i];
0600 
0601         if (!channel->ldb)
0602             continue;
0603 
0604         ret = imx_ldb_register(drm, channel);
0605         if (ret)
0606             return ret;
0607     }
0608 
0609     return 0;
0610 }
0611 
0612 static const struct component_ops imx_ldb_ops = {
0613     .bind   = imx_ldb_bind,
0614 };
0615 
0616 static int imx_ldb_probe(struct platform_device *pdev)
0617 {
0618     struct device *dev = &pdev->dev;
0619     struct device_node *np = dev->of_node;
0620     const struct of_device_id *of_id = of_match_device(imx_ldb_dt_ids, dev);
0621     struct device_node *child;
0622     struct imx_ldb *imx_ldb;
0623     int dual;
0624     int ret;
0625     int i;
0626 
0627     imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
0628     if (!imx_ldb)
0629         return -ENOMEM;
0630 
0631     imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
0632     if (IS_ERR(imx_ldb->regmap)) {
0633         dev_err(dev, "failed to get parent regmap\n");
0634         return PTR_ERR(imx_ldb->regmap);
0635     }
0636 
0637     /* disable LDB by resetting the control register to POR default */
0638     regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
0639 
0640     imx_ldb->dev = dev;
0641 
0642     if (of_id)
0643         imx_ldb->lvds_mux = of_id->data;
0644 
0645     dual = of_property_read_bool(np, "fsl,dual-channel");
0646     if (dual)
0647         imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
0648 
0649     /*
0650      * There are three different possible clock mux configurations:
0651      * i.MX53:  ipu1_di0_sel, ipu1_di1_sel
0652      * i.MX6q:  ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
0653      * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
0654      * Map them all to di0_sel...di3_sel.
0655      */
0656     for (i = 0; i < 4; i++) {
0657         char clkname[16];
0658 
0659         sprintf(clkname, "di%d_sel", i);
0660         imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
0661         if (IS_ERR(imx_ldb->clk_sel[i])) {
0662             ret = PTR_ERR(imx_ldb->clk_sel[i]);
0663             imx_ldb->clk_sel[i] = NULL;
0664             break;
0665         }
0666 
0667         imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
0668     }
0669     if (i == 0)
0670         return ret;
0671 
0672     for_each_child_of_node(np, child) {
0673         struct imx_ldb_channel *channel;
0674         int bus_format;
0675 
0676         ret = of_property_read_u32(child, "reg", &i);
0677         if (ret || i < 0 || i > 1) {
0678             ret = -EINVAL;
0679             goto free_child;
0680         }
0681 
0682         if (!of_device_is_available(child))
0683             continue;
0684 
0685         if (dual && i > 0) {
0686             dev_warn(dev, "dual-channel mode, ignoring second output\n");
0687             continue;
0688         }
0689 
0690         channel = &imx_ldb->channel[i];
0691         channel->ldb = imx_ldb;
0692         channel->chno = i;
0693 
0694         /*
0695          * The output port is port@4 with an external 4-port mux or
0696          * port@2 with the internal 2-port mux.
0697          */
0698         ret = drm_of_find_panel_or_bridge(child,
0699                           imx_ldb->lvds_mux ? 4 : 2, 0,
0700                           &channel->panel, &channel->bridge);
0701         if (ret && ret != -ENODEV)
0702             goto free_child;
0703 
0704         /* panel ddc only if there is no bridge */
0705         if (!channel->bridge) {
0706             ret = imx_ldb_panel_ddc(dev, channel, child);
0707             if (ret)
0708                 goto free_child;
0709         }
0710 
0711         bus_format = of_get_bus_format(dev, child);
0712         if (bus_format == -EINVAL) {
0713             /*
0714              * If no bus format was specified in the device tree,
0715              * we can still get it from the connected panel later.
0716              */
0717             if (channel->panel && channel->panel->funcs &&
0718                 channel->panel->funcs->get_modes)
0719                 bus_format = 0;
0720         }
0721         if (bus_format < 0) {
0722             dev_err(dev, "could not determine data mapping: %d\n",
0723                 bus_format);
0724             ret = bus_format;
0725             goto free_child;
0726         }
0727         channel->bus_format = bus_format;
0728         channel->child = child;
0729     }
0730 
0731     platform_set_drvdata(pdev, imx_ldb);
0732 
0733     return component_add(&pdev->dev, &imx_ldb_ops);
0734 
0735 free_child:
0736     of_node_put(child);
0737     return ret;
0738 }
0739 
0740 static int imx_ldb_remove(struct platform_device *pdev)
0741 {
0742     struct imx_ldb *imx_ldb = platform_get_drvdata(pdev);
0743     int i;
0744 
0745     for (i = 0; i < 2; i++) {
0746         struct imx_ldb_channel *channel = &imx_ldb->channel[i];
0747 
0748         kfree(channel->edid);
0749         i2c_put_adapter(channel->ddc);
0750     }
0751 
0752     component_del(&pdev->dev, &imx_ldb_ops);
0753     return 0;
0754 }
0755 
0756 static struct platform_driver imx_ldb_driver = {
0757     .probe      = imx_ldb_probe,
0758     .remove     = imx_ldb_remove,
0759     .driver     = {
0760         .of_match_table = imx_ldb_dt_ids,
0761         .name   = DRIVER_NAME,
0762     },
0763 };
0764 
0765 module_platform_driver(imx_ldb_driver);
0766 
0767 MODULE_DESCRIPTION("i.MX LVDS driver");
0768 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
0769 MODULE_LICENSE("GPL");
0770 MODULE_ALIAS("platform:" DRIVER_NAME);
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