imx/dcss/dcss-dev.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2019 NXP.
0004  */
0005
0006 #ifndef __DCSS_PRV_H__
0007 #define __DCSS_PRV_H__
0008
0009 #include <drm/drm_fourcc.h>
0010 #include <drm/drm_plane.h>
0011 #include <linux/io.h>
0012 #include <video/videomode.h>
0013
0014 #define SET         0x04
0015 #define CLR         0x08
0016 #define TGL         0x0C
0017
0018 #define dcss_writel(v, c)   writel((v), (c))
0019 #define dcss_readl(c)       readl(c)
0020 #define dcss_set(v, c)      writel((v), (c) + SET)
0021 #define dcss_clr(v, c)      writel((v), (c) + CLR)
0022 #define dcss_toggle(v, c)   writel((v), (c) + TGL)
0023
0024 static inline void dcss_update(u32 v, u32 m, void __iomem *c)
0025 {
0026     writel((readl(c) & ~(m)) | (v), (c));
0027 }
0028
0029 #define DCSS_DBG_REG(reg)   {.name = #reg, .ofs = reg}
0030
0031 enum {
0032     DCSS_IMX8MQ = 0,
0033 };
0034
0035 struct dcss_type_data {
0036     const char *name;
0037     u32 blkctl_ofs;
0038     u32 ctxld_ofs;
0039     u32 rdsrc_ofs;
0040     u32 wrscl_ofs;
0041     u32 dtg_ofs;
0042     u32 scaler_ofs;
0043     u32 ss_ofs;
0044     u32 dpr_ofs;
0045     u32 dtrc_ofs;
0046     u32 dec400d_ofs;
0047     u32 hdr10_ofs;
0048 };
0049
0050 struct dcss_debug_reg {
0051     char *name;
0052     u32 ofs;
0053 };
0054
0055 enum dcss_ctxld_ctx_type {
0056     CTX_DB,
0057     CTX_SB_HP, /* high-priority */
0058     CTX_SB_LP, /* low-priority  */
0059 };
0060
0061 struct dcss_dev {
0062     struct device *dev;
0063     const struct dcss_type_data *devtype;
0064     struct device_node *of_port;
0065
0066     u32 start_addr;
0067
0068     struct dcss_blkctl *blkctl;
0069     struct dcss_ctxld *ctxld;
0070     struct dcss_dpr *dpr;
0071     struct dcss_dtg *dtg;
0072     struct dcss_ss *ss;
0073     struct dcss_hdr10 *hdr10;
0074     struct dcss_scaler *scaler;
0075     struct dcss_dtrc *dtrc;
0076     struct dcss_dec400d *dec400d;
0077     struct dcss_wrscl *wrscl;
0078     struct dcss_rdsrc *rdsrc;
0079
0080     struct clk *apb_clk;
0081     struct clk *axi_clk;
0082     struct clk *pix_clk;
0083     struct clk *rtrm_clk;
0084     struct clk *dtrc_clk;
0085     struct clk *pll_src_clk;
0086     struct clk *pll_phy_ref_clk;
0087
0088     bool hdmi_output;
0089
0090     void (*disable_callback)(void *data);
0091     struct completion disable_completion;
0092 };
0093
0094 struct dcss_dev *dcss_drv_dev_to_dcss(struct device *dev);
0095 struct drm_device *dcss_drv_dev_to_drm(struct device *dev);
0096 struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output);
0097 void dcss_dev_destroy(struct dcss_dev *dcss);
0098 int dcss_dev_runtime_suspend(struct device *dev);
0099 int dcss_dev_runtime_resume(struct device *dev);
0100 int dcss_dev_suspend(struct device *dev);
0101 int dcss_dev_resume(struct device *dev);
0102 void dcss_enable_dtg_and_ss(struct dcss_dev *dcss);
0103 void dcss_disable_dtg_and_ss(struct dcss_dev *dcss);
0104
0105 /* BLKCTL */
0106 int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long blkctl_base);
0107 void dcss_blkctl_cfg(struct dcss_blkctl *blkctl);
0108 void dcss_blkctl_exit(struct dcss_blkctl *blkctl);
0109
0110 /* CTXLD */
0111 int dcss_ctxld_init(struct dcss_dev *dcss, unsigned long ctxld_base);
0112 void dcss_ctxld_exit(struct dcss_ctxld *ctxld);
0113 void dcss_ctxld_write(struct dcss_ctxld *ctxld, u32 ctx_id,
0114               u32 val, u32 reg_idx);
0115 int dcss_ctxld_resume(struct dcss_ctxld *dcss_ctxld);
0116 int dcss_ctxld_suspend(struct dcss_ctxld *dcss_ctxld);
0117 void dcss_ctxld_write_irqsafe(struct dcss_ctxld *ctlxd, u32 ctx_id, u32 val,
0118                   u32 reg_ofs);
0119 void dcss_ctxld_kick(struct dcss_ctxld *ctxld);
0120 bool dcss_ctxld_is_flushed(struct dcss_ctxld *ctxld);
0121 int dcss_ctxld_enable(struct dcss_ctxld *ctxld);
0122 void dcss_ctxld_register_completion(struct dcss_ctxld *ctxld,
0123                     struct completion *dis_completion);
0124 void dcss_ctxld_assert_locked(struct dcss_ctxld *ctxld);
0125
0126 /* DPR */
0127 int dcss_dpr_init(struct dcss_dev *dcss, unsigned long dpr_base);
0128 void dcss_dpr_exit(struct dcss_dpr *dpr);
0129 void dcss_dpr_write_sysctrl(struct dcss_dpr *dpr);
0130 void dcss_dpr_set_res(struct dcss_dpr *dpr, int ch_num, u32 xres, u32 yres);
0131 void dcss_dpr_addr_set(struct dcss_dpr *dpr, int ch_num, u32 luma_base_addr,
0132                u32 chroma_base_addr, u16 pitch);
0133 void dcss_dpr_enable(struct dcss_dpr *dpr, int ch_num, bool en);
0134 void dcss_dpr_format_set(struct dcss_dpr *dpr, int ch_num,
0135              const struct drm_format_info *format, u64 modifier);
0136 void dcss_dpr_set_rotation(struct dcss_dpr *dpr, int ch_num, u32 rotation);
0137
0138 /* DTG */
0139 int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base);
0140 void dcss_dtg_exit(struct dcss_dtg *dtg);
0141 bool dcss_dtg_vblank_irq_valid(struct dcss_dtg *dtg);
0142 void dcss_dtg_vblank_irq_enable(struct dcss_dtg *dtg, bool en);
0143 void dcss_dtg_vblank_irq_clear(struct dcss_dtg *dtg);
0144 void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm);
0145 void dcss_dtg_css_set(struct dcss_dtg *dtg);
0146 void dcss_dtg_enable(struct dcss_dtg *dtg);
0147 void dcss_dtg_shutoff(struct dcss_dtg *dtg);
0148 bool dcss_dtg_is_enabled(struct dcss_dtg *dtg);
0149 void dcss_dtg_ctxld_kick_irq_enable(struct dcss_dtg *dtg, bool en);
0150 bool dcss_dtg_global_alpha_changed(struct dcss_dtg *dtg, int ch_num, int alpha);
0151 void dcss_dtg_plane_alpha_set(struct dcss_dtg *dtg, int ch_num,
0152                   const struct drm_format_info *format, int alpha);
0153 void dcss_dtg_plane_pos_set(struct dcss_dtg *dtg, int ch_num,
0154                 int px, int py, int pw, int ph);
0155 void dcss_dtg_ch_enable(struct dcss_dtg *dtg, int ch_num, bool en);
0156
0157 /* SUBSAM */
0158 int dcss_ss_init(struct dcss_dev *dcss, unsigned long subsam_base);
0159 void dcss_ss_exit(struct dcss_ss *ss);
0160 void dcss_ss_enable(struct dcss_ss *ss);
0161 void dcss_ss_shutoff(struct dcss_ss *ss);
0162 void dcss_ss_subsam_set(struct dcss_ss *ss);
0163 void dcss_ss_sync_set(struct dcss_ss *ss, struct videomode *vm,
0164               bool phsync, bool pvsync);
0165
0166 /* SCALER */
0167 int dcss_scaler_init(struct dcss_dev *dcss, unsigned long scaler_base);
0168 void dcss_scaler_exit(struct dcss_scaler *scl);
0169 void dcss_scaler_set_filter(struct dcss_scaler *scl, int ch_num,
0170                 enum drm_scaling_filter scaling_filter);
0171 void dcss_scaler_setup(struct dcss_scaler *scl, int ch_num,
0172                const struct drm_format_info *format,
0173                int src_xres, int src_yres, int dst_xres, int dst_yres,
0174                u32 vrefresh_hz);
0175 void dcss_scaler_ch_enable(struct dcss_scaler *scl, int ch_num, bool en);
0176 int dcss_scaler_get_min_max_ratios(struct dcss_scaler *scl, int ch_num,
0177                    int *min, int *max);
0178 void dcss_scaler_write_sclctrl(struct dcss_scaler *scl);
0179
0180 #endif /* __DCSS_PRV_H__ */