drm/i915/intel_step.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2020,2021 Intel Corporation
0004  */
0005
0006 #include "i915_drv.h"
0007 #include "intel_step.h"
0008
0009 /*
0010  * Some platforms have unusual ways of mapping PCI revision ID to GT/display
0011  * steppings.  E.g., in some cases a higher PCI revision may translate to a
0012  * lower stepping of the GT and/or display IP.  This file provides lookup
0013  * tables to map the PCI revision into a standard set of stepping values that
0014  * can be compared numerically.
0015  *
0016  * Also note that some revisions/steppings may have been set aside as
0017  * placeholders but never materialized in real hardware; in those cases there
0018  * may be jumps in the revision IDs or stepping values in the tables below.
0019  */
0020
0021 /*
0022  * Some platforms always have the same stepping value for GT and display;
0023  * use a macro to define these to make it easier to identify the platforms
0024  * where the two steppings can deviate.
0025  */
0026 #define COMMON_STEP(x)  .graphics_step = STEP_##x, .display_step = STEP_##x, .media_step = STEP_##x
0027 #define COMMON_GT_MEDIA_STEP(x)  .graphics_step = STEP_##x, .media_step = STEP_##x
0028
0029 static const struct intel_step_info skl_revids[] = {
0030     [0x6] = { COMMON_STEP(G0) },
0031     [0x7] = { COMMON_STEP(H0) },
0032     [0x9] = { COMMON_STEP(J0) },
0033     [0xA] = { COMMON_STEP(I1) },
0034 };
0035
0036 static const struct intel_step_info kbl_revids[] = {
0037     [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
0038     [2] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 },
0039     [3] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_B0 },
0040     [4] = { COMMON_GT_MEDIA_STEP(F0), .display_step = STEP_C0 },
0041     [5] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B1 },
0042     [6] = { COMMON_GT_MEDIA_STEP(D1), .display_step = STEP_B1 },
0043     [7] = { COMMON_GT_MEDIA_STEP(G0), .display_step = STEP_C0 },
0044 };
0045
0046 static const struct intel_step_info bxt_revids[] = {
0047     [0xA] = { COMMON_STEP(C0) },
0048     [0xB] = { COMMON_STEP(C0) },
0049     [0xC] = { COMMON_STEP(D0) },
0050     [0xD] = { COMMON_STEP(E0) },
0051 };
0052
0053 static const struct intel_step_info glk_revids[] = {
0054     [3] = { COMMON_STEP(B0) },
0055 };
0056
0057 static const struct intel_step_info icl_revids[] = {
0058     [7] = { COMMON_STEP(D0) },
0059 };
0060
0061 static const struct intel_step_info jsl_ehl_revids[] = {
0062     [0] = { COMMON_STEP(A0) },
0063     [1] = { COMMON_STEP(B0) },
0064 };
0065
0066 static const struct intel_step_info tgl_uy_revids[] = {
0067     [0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
0068     [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 },
0069     [2] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
0070     [3] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
0071 };
0072
0073 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
0074 static const struct intel_step_info tgl_revids[] = {
0075     [0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 },
0076     [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_D0 },
0077 };
0078
0079 static const struct intel_step_info rkl_revids[] = {
0080     [0] = { COMMON_STEP(A0) },
0081     [1] = { COMMON_STEP(B0) },
0082     [4] = { COMMON_STEP(C0) },
0083 };
0084
0085 static const struct intel_step_info dg1_revids[] = {
0086     [0] = { COMMON_STEP(A0) },
0087     [1] = { COMMON_STEP(B0) },
0088 };
0089
0090 static const struct intel_step_info adls_revids[] = {
0091     [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
0092     [0x1] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A2 },
0093     [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
0094     [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 },
0095     [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
0096 };
0097
0098 static const struct intel_step_info adlp_revids[] = {
0099     [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
0100     [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
0101     [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 },
0102     [0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
0103 };
0104
0105 static const struct intel_step_info xehpsdv_revids[] = {
0106     [0x0] = { COMMON_GT_MEDIA_STEP(A0) },
0107     [0x1] = { COMMON_GT_MEDIA_STEP(A1) },
0108     [0x4] = { COMMON_GT_MEDIA_STEP(B0) },
0109     [0x8] = { COMMON_GT_MEDIA_STEP(C0) },
0110 };
0111
0112 static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
0113     [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
0114     [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 },
0115     [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
0116     [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 },
0117 };
0118
0119 static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
0120     [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 },
0121     [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 },
0122     [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
0123 };
0124
0125 static const struct intel_step_info dg2_g12_revid_step_tbl[] = {
0126     [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 },
0127 };
0128
0129 static const struct intel_step_info adls_rpls_revids[] = {
0130     [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
0131     [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
0132 };
0133
0134 static const struct intel_step_info adlp_n_revids[] = {
0135     [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
0136 };
0137
0138 static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
0139
0140 void intel_step_init(struct drm_i915_private *i915)
0141 {
0142     const struct intel_step_info *revids = NULL;
0143     int size = 0;
0144     int revid = INTEL_REVID(i915);
0145     struct intel_step_info step = {};
0146
0147     if (IS_PONTEVECCHIO(i915)) {
0148         pvc_step_init(i915, revid);
0149         return;
0150     } else if (IS_DG2_G10(i915)) {
0151         revids = dg2_g10_revid_step_tbl;
0152         size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
0153     } else if (IS_DG2_G11(i915)) {
0154         revids = dg2_g11_revid_step_tbl;
0155         size = ARRAY_SIZE(dg2_g11_revid_step_tbl);
0156     } else if (IS_DG2_G12(i915)) {
0157         revids = dg2_g12_revid_step_tbl;
0158         size = ARRAY_SIZE(dg2_g12_revid_step_tbl);
0159     } else if (IS_XEHPSDV(i915)) {
0160         revids = xehpsdv_revids;
0161         size = ARRAY_SIZE(xehpsdv_revids);
0162     } else if (IS_ADLP_N(i915)) {
0163         revids = adlp_n_revids;
0164         size = ARRAY_SIZE(adlp_n_revids);
0165     } else if (IS_ALDERLAKE_P(i915)) {
0166         revids = adlp_revids;
0167         size = ARRAY_SIZE(adlp_revids);
0168     } else if (IS_ADLS_RPLS(i915)) {
0169         revids = adls_rpls_revids;
0170         size = ARRAY_SIZE(adls_rpls_revids);
0171     } else if (IS_ALDERLAKE_S(i915)) {
0172         revids = adls_revids;
0173         size = ARRAY_SIZE(adls_revids);
0174     } else if (IS_DG1(i915)) {
0175         revids = dg1_revids;
0176         size = ARRAY_SIZE(dg1_revids);
0177     } else if (IS_ROCKETLAKE(i915)) {
0178         revids = rkl_revids;
0179         size = ARRAY_SIZE(rkl_revids);
0180     } else if (IS_TGL_UY(i915)) {
0181         revids = tgl_uy_revids;
0182         size = ARRAY_SIZE(tgl_uy_revids);
0183     } else if (IS_TIGERLAKE(i915)) {
0184         revids = tgl_revids;
0185         size = ARRAY_SIZE(tgl_revids);
0186     } else if (IS_JSL_EHL(i915)) {
0187         revids = jsl_ehl_revids;
0188         size = ARRAY_SIZE(jsl_ehl_revids);
0189     } else if (IS_ICELAKE(i915)) {
0190         revids = icl_revids;
0191         size = ARRAY_SIZE(icl_revids);
0192     } else if (IS_GEMINILAKE(i915)) {
0193         revids = glk_revids;
0194         size = ARRAY_SIZE(glk_revids);
0195     } else if (IS_BROXTON(i915)) {
0196         revids = bxt_revids;
0197         size = ARRAY_SIZE(bxt_revids);
0198     } else if (IS_KABYLAKE(i915)) {
0199         revids = kbl_revids;
0200         size = ARRAY_SIZE(kbl_revids);
0201     } else if (IS_SKYLAKE(i915)) {
0202         revids = skl_revids;
0203         size = ARRAY_SIZE(skl_revids);
0204     }
0205
0206     /* Not using the stepping scheme for the platform yet. */
0207     if (!revids)
0208         return;
0209
0210     if (revid < size && revids[revid].graphics_step != STEP_NONE) {
0211         step = revids[revid];
0212     } else {
0213         drm_warn(&i915->drm, "Unknown revid 0x%02x\n", revid);
0214
0215         /*
0216          * If we hit a gap in the revid array, use the information for
0217          * the next revid.
0218          *
0219          * This may be wrong in all sorts of ways, especially if the
0220          * steppings in the array are not monotonically increasing, but
0221          * it's better than defaulting to 0.
0222          */
0223         while (revid < size && revids[revid].graphics_step == STEP_NONE)
0224             revid++;
0225
0226         if (revid < size) {
0227             drm_dbg(&i915->drm, "Using steppings for revid 0x%02x\n",
0228                 revid);
0229             step = revids[revid];
0230         } else {
0231             drm_dbg(&i915->drm, "Using future steppings\n");
0232             step.graphics_step = STEP_FUTURE;
0233             step.display_step = STEP_FUTURE;
0234         }
0235     }
0236
0237     if (drm_WARN_ON(&i915->drm, step.graphics_step == STEP_NONE))
0238         return;
0239
0240     RUNTIME_INFO(i915)->step = step;
0241 }
0242
0243 #define PVC_BD_REVID    GENMASK(5, 3)
0244 #define PVC_CT_REVID    GENMASK(2, 0)
0245
0246 static const int pvc_bd_subids[] = {
0247     [0x0] = STEP_A0,
0248     [0x3] = STEP_B0,
0249     [0x4] = STEP_B1,
0250     [0x5] = STEP_B3,
0251 };
0252
0253 static const int pvc_ct_subids[] = {
0254     [0x3] = STEP_A0,
0255     [0x5] = STEP_B0,
0256     [0x6] = STEP_B1,
0257     [0x7] = STEP_C0,
0258 };
0259
0260 static int
0261 pvc_step_lookup(struct drm_i915_private *i915, const char *type,
0262         const int *table, int size, int subid)
0263 {
0264     if (subid < size && table[subid] != STEP_NONE)
0265         return table[subid];
0266
0267     drm_warn(&i915->drm, "Unknown %s id 0x%02x\n", type, subid);
0268
0269     /*
0270      * As on other platforms, try to use the next higher ID if we land on a
0271      * gap in the table.
0272      */
0273     while (subid < size && table[subid] == STEP_NONE)
0274         subid++;
0275
0276     if (subid < size) {
0277         drm_dbg(&i915->drm, "Using steppings for %s id 0x%02x\n",
0278             type, subid);
0279         return table[subid];
0280     }
0281
0282     drm_dbg(&i915->drm, "Using future steppings\n");
0283     return STEP_FUTURE;
0284 }
0285
0286 /*
0287  * PVC needs special handling since we don't lookup the
0288  * revid in a table, but rather specific bitfields within
0289  * the revid for various components.
0290  */
0291 static void pvc_step_init(struct drm_i915_private *i915, int pci_revid)
0292 {
0293     int ct_subid, bd_subid;
0294
0295     bd_subid = FIELD_GET(PVC_BD_REVID, pci_revid);
0296     ct_subid = FIELD_GET(PVC_CT_REVID, pci_revid);
0297
0298     RUNTIME_INFO(i915)->step.basedie_step =
0299         pvc_step_lookup(i915, "Base Die", pvc_bd_subids,
0300                 ARRAY_SIZE(pvc_bd_subids), bd_subid);
0301     RUNTIME_INFO(i915)->step.graphics_step =
0302         pvc_step_lookup(i915, "Compute Tile", pvc_ct_subids,
0303                 ARRAY_SIZE(pvc_ct_subids), ct_subid);
0304 }
0305
0306 #define STEP_NAME_CASE(name)    \
0307     case STEP_##name:   \
0308         return #name;
0309
0310 const char *intel_step_name(enum intel_step step)
0311 {
0312     switch (step) {
0313     STEP_NAME_LIST(STEP_NAME_CASE);
0314
0315     default:
0316         return "**";
0317     }
0318 }