drm/i915/intel_sbi.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2013-2021 Intel Corporation
0004  *
0005  * LPT/WPT IOSF sideband.
0006  */
0007
0008 #include "i915_drv.h"
0009 #include "intel_sbi.h"
0010 #include "i915_reg.h"
0011
0012 /* SBI access */
0013 static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
0014             enum intel_sbi_destination destination,
0015             u32 *val, bool is_read)
0016 {
0017     struct intel_uncore *uncore = &i915->uncore;
0018     u32 cmd;
0019
0020     lockdep_assert_held(&i915->sb_lock);
0021
0022     if (intel_wait_for_register_fw(uncore,
0023                        SBI_CTL_STAT, SBI_BUSY, 0,
0024                        100)) {
0025         drm_err(&i915->drm,
0026             "timeout waiting for SBI to become ready\n");
0027         return -EBUSY;
0028     }
0029
0030     intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
0031     intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
0032
0033     if (destination == SBI_ICLK)
0034         cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
0035     else
0036         cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
0037     if (!is_read)
0038         cmd |= BIT(8);
0039     intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
0040
0041     if (__intel_wait_for_register_fw(uncore,
0042                      SBI_CTL_STAT, SBI_BUSY, 0,
0043                      100, 100, &cmd)) {
0044         drm_err(&i915->drm,
0045             "timeout waiting for SBI to complete read\n");
0046         return -ETIMEDOUT;
0047     }
0048
0049     if (cmd & SBI_RESPONSE_FAIL) {
0050         drm_err(&i915->drm, "error during SBI read of reg %x\n", reg);
0051         return -ENXIO;
0052     }
0053
0054     if (is_read)
0055         *val = intel_uncore_read_fw(uncore, SBI_DATA);
0056
0057     return 0;
0058 }
0059
0060 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
0061            enum intel_sbi_destination destination)
0062 {
0063     u32 result = 0;
0064
0065     intel_sbi_rw(i915, reg, destination, &result, true);
0066
0067     return result;
0068 }
0069
0070 void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
0071              enum intel_sbi_destination destination)
0072 {
0073     intel_sbi_rw(i915, reg, destination, &value, false);
0074 }