drm/i915/intel_pm.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_PM_H__
0007 #define __INTEL_PM_H__
0008
0009 #include <linux/types.h>
0010
0011 #include "display/intel_display.h"
0012 #include "display/intel_global_state.h"
0013
0014 #include "i915_drv.h"
0015
0016 struct drm_device;
0017 struct drm_i915_private;
0018 struct i915_request;
0019 struct intel_atomic_state;
0020 struct intel_bw_state;
0021 struct intel_crtc;
0022 struct intel_crtc_state;
0023 struct intel_plane;
0024 struct skl_ddb_entry;
0025 struct skl_pipe_wm;
0026 struct skl_wm_level;
0027
0028 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
0029 void intel_suspend_hw(struct drm_i915_private *dev_priv);
0030 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
0031 void intel_init_pm(struct drm_i915_private *dev_priv);
0032 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
0033 void intel_pm_setup(struct drm_i915_private *dev_priv);
0034 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
0035 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
0036 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
0037 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
0038 void intel_wm_state_verify(struct intel_crtc *crtc,
0039                struct intel_crtc_state *new_crtc_state);
0040 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
0041 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
0042 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
0043                 const struct skl_ddb_entry *entry);
0044 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
0045 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
0046 void skl_wm_sanitize(struct drm_i915_private *dev_priv);
0047 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
0048                const struct intel_bw_state *bw_state);
0049 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
0050 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
0051 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
0052                  const struct skl_ddb_entry *entries,
0053                  int num_entries, int ignore_idx);
0054 void skl_write_plane_wm(struct intel_plane *plane,
0055             const struct intel_crtc_state *crtc_state);
0056 void skl_write_cursor_wm(struct intel_plane *plane,
0057              const struct intel_crtc_state *crtc_state);
0058 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
0059 void intel_init_ipc(struct drm_i915_private *dev_priv);
0060 void intel_enable_ipc(struct drm_i915_private *dev_priv);
0061
0062 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
0063
0064 struct intel_dbuf_state {
0065     struct intel_global_state base;
0066
0067     struct skl_ddb_entry ddb[I915_MAX_PIPES];
0068     unsigned int weight[I915_MAX_PIPES];
0069     u8 slices[I915_MAX_PIPES];
0070     u8 enabled_slices;
0071     u8 active_pipes;
0072     bool joined_mbus;
0073 };
0074
0075 struct intel_dbuf_state *
0076 intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
0077
0078 #define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
0079 #define intel_atomic_get_old_dbuf_state(state) \
0080     to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
0081 #define intel_atomic_get_new_dbuf_state(state) \
0082     to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
0083
0084 int intel_dbuf_init(struct drm_i915_private *dev_priv);
0085 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
0086 void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
0087 void intel_mbus_dbox_update(struct intel_atomic_state *state);
0088
0089 #endif /* __INTEL_PM_H__ */