drm/i915/intel_pci_config.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_PCI_CONFIG_H__
0007 #define __INTEL_PCI_CONFIG_H__
0008
0009 /* BSM in include/drm/i915_drm.h */
0010
0011 #define MCHBAR_I915             0x44
0012 #define MCHBAR_I965             0x48
0013 #define   MCHBAR_SIZE               (4 * 4096)
0014
0015 #define DEVEN                   0x54
0016 #define   DEVEN_MCHBAR_EN           (1 << 28)
0017
0018 #define HPLLCC                  0xc0 /* 85x only */
0019 #define   GC_CLOCK_CONTROL_MASK         (0x7 << 0)
0020 #define   GC_CLOCK_133_200          (0 << 0)
0021 #define   GC_CLOCK_100_200          (1 << 0)
0022 #define   GC_CLOCK_100_133          (2 << 0)
0023 #define   GC_CLOCK_133_266          (3 << 0)
0024 #define   GC_CLOCK_133_200_2            (4 << 0)
0025 #define   GC_CLOCK_133_266_2            (5 << 0)
0026 #define   GC_CLOCK_166_266          (6 << 0)
0027 #define   GC_CLOCK_166_250          (7 << 0)
0028
0029 #define I915_GDRST              0xc0
0030 #define   GRDOM_FULL                (0 << 2)
0031 #define   GRDOM_RENDER              (1 << 2)
0032 #define   GRDOM_MEDIA               (3 << 2)
0033 #define   GRDOM_MASK                (3 << 2)
0034 #define   GRDOM_RESET_STATUS            (1 << 1)
0035 #define   GRDOM_RESET_ENABLE            (1 << 0)
0036
0037 /* BSpec only has register offset, PCI device and bit found empirically */
0038 #define I830_CLOCK_GATE             0xc8 /* device 0 */
0039 #define   I830_L2_CACHE_CLOCK_GATE_DISABLE  (1 << 2)
0040
0041 #define GCDGMBUS                0xcc
0042
0043 #define GCFGC2                  0xda
0044 #define GCFGC                   0xf0 /* 915+ only */
0045 #define   GC_LOW_FREQUENCY_ENABLE       (1 << 7)
0046 #define   GC_DISPLAY_CLOCK_190_200_MHZ      (0 << 4)
0047 #define   GC_DISPLAY_CLOCK_333_320_MHZ      (4 << 4)
0048 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV      (0 << 4)
0049 #define   GC_DISPLAY_CLOCK_333_MHZ_PNV      (1 << 4)
0050 #define   GC_DISPLAY_CLOCK_444_MHZ_PNV      (2 << 4)
0051 #define   GC_DISPLAY_CLOCK_200_MHZ_PNV      (5 << 4)
0052 #define   GC_DISPLAY_CLOCK_133_MHZ_PNV      (6 << 4)
0053 #define   GC_DISPLAY_CLOCK_167_MHZ_PNV      (7 << 4)
0054 #define   GC_DISPLAY_CLOCK_MASK         (7 << 4)
0055 #define   GM45_GC_RENDER_CLOCK_MASK     (0xf << 0)
0056 #define   GM45_GC_RENDER_CLOCK_266_MHZ      (8 << 0)
0057 #define   GM45_GC_RENDER_CLOCK_320_MHZ      (9 << 0)
0058 #define   GM45_GC_RENDER_CLOCK_400_MHZ      (0xb << 0)
0059 #define   GM45_GC_RENDER_CLOCK_533_MHZ      (0xc << 0)
0060 #define   I965_GC_RENDER_CLOCK_MASK     (0xf << 0)
0061 #define   I965_GC_RENDER_CLOCK_267_MHZ      (2 << 0)
0062 #define   I965_GC_RENDER_CLOCK_333_MHZ      (3 << 0)
0063 #define   I965_GC_RENDER_CLOCK_444_MHZ      (4 << 0)
0064 #define   I965_GC_RENDER_CLOCK_533_MHZ      (5 << 0)
0065 #define   I945_GC_RENDER_CLOCK_MASK     (7 << 0)
0066 #define   I945_GC_RENDER_CLOCK_166_MHZ      (0 << 0)
0067 #define   I945_GC_RENDER_CLOCK_200_MHZ      (1 << 0)
0068 #define   I945_GC_RENDER_CLOCK_250_MHZ      (3 << 0)
0069 #define   I945_GC_RENDER_CLOCK_400_MHZ      (5 << 0)
0070 #define   I915_GC_RENDER_CLOCK_MASK     (7 << 0)
0071 #define   I915_GC_RENDER_CLOCK_166_MHZ      (0 << 0)
0072 #define   I915_GC_RENDER_CLOCK_200_MHZ      (1 << 0)
0073 #define   I915_GC_RENDER_CLOCK_333_MHZ      (4 << 0)
0074
0075 #define ASLE                    0xe4
0076 #define ASLS                    0xfc
0077
0078 #define SWSCI                   0xe8
0079 #define   SWSCI_SCISEL              (1 << 15)
0080 #define   SWSCI_GSSCIE              (1 << 0)
0081
0082 /* legacy/combination backlight modes, also called LBB */
0083 #define LBPC                    0xf4
0084
0085 #endif /* __INTEL_PCI_CONFIG_H__ */