drm/i915/intel_pch.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright 2019 Intel Corporation.
0004  */
0005
0006 #ifndef __INTEL_PCH__
0007 #define __INTEL_PCH__
0008
0009 struct drm_i915_private;
0010
0011 /*
0012  * Sorted by south display engine compatibility.
0013  * If the new PCH comes with a south display engine that is not
0014  * inherited from the latest item, please do not add it to the
0015  * end. Instead, add it right after its "parent" PCH.
0016  */
0017 enum intel_pch {
0018     PCH_NOP = -1,   /* PCH without south display */
0019     PCH_NONE = 0,   /* No PCH present */
0020     PCH_IBX,    /* Ibexpeak PCH */
0021     PCH_CPT,    /* Cougarpoint/Pantherpoint PCH */
0022     PCH_LPT,    /* Lynxpoint/Wildcatpoint PCH */
0023     PCH_SPT,        /* Sunrisepoint/Kaby Lake PCH */
0024     PCH_CNP,        /* Cannon/Comet Lake PCH */
0025     PCH_ICP,    /* Ice Lake/Jasper Lake PCH */
0026     PCH_TGP,    /* Tiger Lake/Mule Creek Canyon PCH */
0027     PCH_ADP,    /* Alder Lake PCH */
0028
0029     /* Fake PCHs, functionality handled on the same PCI dev */
0030     PCH_DG1 = 1024,
0031     PCH_DG2,
0032 };
0033
0034 #define INTEL_PCH_DEVICE_ID_MASK        0xff80
0035 #define INTEL_PCH_IBX_DEVICE_ID_TYPE        0x3b00
0036 #define INTEL_PCH_CPT_DEVICE_ID_TYPE        0x1c00
0037 #define INTEL_PCH_PPT_DEVICE_ID_TYPE        0x1e00
0038 #define INTEL_PCH_LPT_DEVICE_ID_TYPE        0x8c00
0039 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE     0x9c00
0040 #define INTEL_PCH_WPT_DEVICE_ID_TYPE        0x8c80
0041 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE     0x9c80
0042 #define INTEL_PCH_SPT_DEVICE_ID_TYPE        0xA100
0043 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE     0x9D00
0044 #define INTEL_PCH_KBP_DEVICE_ID_TYPE        0xA280
0045 #define INTEL_PCH_CNP_DEVICE_ID_TYPE        0xA300
0046 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE     0x9D80
0047 #define INTEL_PCH_CMP_DEVICE_ID_TYPE        0x0280
0048 #define INTEL_PCH_CMP2_DEVICE_ID_TYPE       0x0680
0049 #define INTEL_PCH_CMP_V_DEVICE_ID_TYPE      0xA380
0050 #define INTEL_PCH_ICP_DEVICE_ID_TYPE        0x3480
0051 #define INTEL_PCH_ICP2_DEVICE_ID_TYPE       0x3880
0052 #define INTEL_PCH_MCC_DEVICE_ID_TYPE        0x4B00
0053 #define INTEL_PCH_TGP_DEVICE_ID_TYPE        0xA080
0054 #define INTEL_PCH_TGP2_DEVICE_ID_TYPE       0x4380
0055 #define INTEL_PCH_JSP_DEVICE_ID_TYPE        0x4D80
0056 #define INTEL_PCH_ADP_DEVICE_ID_TYPE        0x7A80
0057 #define INTEL_PCH_ADP2_DEVICE_ID_TYPE       0x5180
0058 #define INTEL_PCH_ADP3_DEVICE_ID_TYPE       0x7A00
0059 #define INTEL_PCH_ADP4_DEVICE_ID_TYPE       0x5480
0060 #define INTEL_PCH_P2X_DEVICE_ID_TYPE        0x7100
0061 #define INTEL_PCH_P3X_DEVICE_ID_TYPE        0x7000
0062 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE       0x2900 /* qemu q35 has 2918 */
0063
0064 #define INTEL_PCH_TYPE(dev_priv)        ((dev_priv)->pch_type)
0065 #define INTEL_PCH_ID(dev_priv)          ((dev_priv)->pch_id)
0066 #define HAS_PCH_DG2(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
0067 #define HAS_PCH_ADP(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
0068 #define HAS_PCH_DG1(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
0069 #define HAS_PCH_TGP(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
0070 #define HAS_PCH_ICP(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
0071 #define HAS_PCH_CNP(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
0072 #define HAS_PCH_SPT(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
0073 #define HAS_PCH_LPT(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
0074 #define HAS_PCH_LPT_LP(dev_priv) \
0075     (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
0076      INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
0077 #define HAS_PCH_LPT_H(dev_priv) \
0078     (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
0079      INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
0080 #define HAS_PCH_CPT(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
0081 #define HAS_PCH_IBX(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
0082 #define HAS_PCH_NOP(dev_priv)           (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
0083 #define HAS_PCH_SPLIT(dev_priv)         (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
0084
0085 void intel_detect_pch(struct drm_i915_private *dev_priv);
0086
0087 #endif /* __INTEL_PCH__ */