drm/i915/intel_dram.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2020 Intel Corporation
0004  */
0005
0006 #include <linux/string_helpers.h>
0007
0008 #include "i915_drv.h"
0009 #include "i915_reg.h"
0010 #include "intel_dram.h"
0011 #include "intel_mchbar_regs.h"
0012 #include "intel_pcode.h"
0013
0014 struct dram_dimm_info {
0015     u16 size;
0016     u8 width, ranks;
0017 };
0018
0019 struct dram_channel_info {
0020     struct dram_dimm_info dimm_l, dimm_s;
0021     u8 ranks;
0022     bool is_16gb_dimm;
0023 };
0024
0025 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
0026
0027 static const char *intel_dram_type_str(enum intel_dram_type type)
0028 {
0029     static const char * const str[] = {
0030         DRAM_TYPE_STR(UNKNOWN),
0031         DRAM_TYPE_STR(DDR3),
0032         DRAM_TYPE_STR(DDR4),
0033         DRAM_TYPE_STR(LPDDR3),
0034         DRAM_TYPE_STR(LPDDR4),
0035     };
0036
0037     if (type >= ARRAY_SIZE(str))
0038         type = INTEL_DRAM_UNKNOWN;
0039
0040     return str[type];
0041 }
0042
0043 #undef DRAM_TYPE_STR
0044
0045 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
0046 {
0047     return dimm->ranks * 64 / (dimm->width ?: 1);
0048 }
0049
0050 /* Returns total Gb for the whole DIMM */
0051 static int skl_get_dimm_size(u16 val)
0052 {
0053     return (val & SKL_DRAM_SIZE_MASK) * 8;
0054 }
0055
0056 static int skl_get_dimm_width(u16 val)
0057 {
0058     if (skl_get_dimm_size(val) == 0)
0059         return 0;
0060
0061     switch (val & SKL_DRAM_WIDTH_MASK) {
0062     case SKL_DRAM_WIDTH_X8:
0063     case SKL_DRAM_WIDTH_X16:
0064     case SKL_DRAM_WIDTH_X32:
0065         val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
0066         return 8 << val;
0067     default:
0068         MISSING_CASE(val);
0069         return 0;
0070     }
0071 }
0072
0073 static int skl_get_dimm_ranks(u16 val)
0074 {
0075     if (skl_get_dimm_size(val) == 0)
0076         return 0;
0077
0078     val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
0079
0080     return val + 1;
0081 }
0082
0083 /* Returns total Gb for the whole DIMM */
0084 static int icl_get_dimm_size(u16 val)
0085 {
0086     return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
0087 }
0088
0089 static int icl_get_dimm_width(u16 val)
0090 {
0091     if (icl_get_dimm_size(val) == 0)
0092         return 0;
0093
0094     switch (val & ICL_DRAM_WIDTH_MASK) {
0095     case ICL_DRAM_WIDTH_X8:
0096     case ICL_DRAM_WIDTH_X16:
0097     case ICL_DRAM_WIDTH_X32:
0098         val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
0099         return 8 << val;
0100     default:
0101         MISSING_CASE(val);
0102         return 0;
0103     }
0104 }
0105
0106 static int icl_get_dimm_ranks(u16 val)
0107 {
0108     if (icl_get_dimm_size(val) == 0)
0109         return 0;
0110
0111     val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
0112
0113     return val + 1;
0114 }
0115
0116 static bool
0117 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
0118 {
0119     /* Convert total Gb to Gb per DRAM device */
0120     return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
0121 }
0122
0123 static void
0124 skl_dram_get_dimm_info(struct drm_i915_private *i915,
0125                struct dram_dimm_info *dimm,
0126                int channel, char dimm_name, u16 val)
0127 {
0128     if (GRAPHICS_VER(i915) >= 11) {
0129         dimm->size = icl_get_dimm_size(val);
0130         dimm->width = icl_get_dimm_width(val);
0131         dimm->ranks = icl_get_dimm_ranks(val);
0132     } else {
0133         dimm->size = skl_get_dimm_size(val);
0134         dimm->width = skl_get_dimm_width(val);
0135         dimm->ranks = skl_get_dimm_ranks(val);
0136     }
0137
0138     drm_dbg_kms(&i915->drm,
0139             "CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
0140             channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
0141             str_yes_no(skl_is_16gb_dimm(dimm)));
0142 }
0143
0144 static int
0145 skl_dram_get_channel_info(struct drm_i915_private *i915,
0146               struct dram_channel_info *ch,
0147               int channel, u32 val)
0148 {
0149     skl_dram_get_dimm_info(i915, &ch->dimm_l,
0150                    channel, 'L', val & 0xffff);
0151     skl_dram_get_dimm_info(i915, &ch->dimm_s,
0152                    channel, 'S', val >> 16);
0153
0154     if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
0155         drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
0156         return -EINVAL;
0157     }
0158
0159     if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
0160         ch->ranks = 2;
0161     else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
0162         ch->ranks = 2;
0163     else
0164         ch->ranks = 1;
0165
0166     ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||
0167         skl_is_16gb_dimm(&ch->dimm_s);
0168
0169     drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
0170             channel, ch->ranks, str_yes_no(ch->is_16gb_dimm));
0171
0172     return 0;
0173 }
0174
0175 static bool
0176 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
0177             const struct dram_channel_info *ch1)
0178 {
0179     return !memcmp(ch0, ch1, sizeof(*ch0)) &&
0180         (ch0->dimm_s.size == 0 ||
0181          !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
0182 }
0183
0184 static int
0185 skl_dram_get_channels_info(struct drm_i915_private *i915)
0186 {
0187     struct dram_info *dram_info = &i915->dram_info;
0188     struct dram_channel_info ch0 = {}, ch1 = {};
0189     u32 val;
0190     int ret;
0191
0192     val = intel_uncore_read(&i915->uncore,
0193                 SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
0194     ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
0195     if (ret == 0)
0196         dram_info->num_channels++;
0197
0198     val = intel_uncore_read(&i915->uncore,
0199                 SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
0200     ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
0201     if (ret == 0)
0202         dram_info->num_channels++;
0203
0204     if (dram_info->num_channels == 0) {
0205         drm_info(&i915->drm, "Number of memory channels is zero\n");
0206         return -EINVAL;
0207     }
0208
0209     if (ch0.ranks == 0 && ch1.ranks == 0) {
0210         drm_info(&i915->drm, "couldn't get memory rank information\n");
0211         return -EINVAL;
0212     }
0213
0214     dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
0215
0216     dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
0217
0218     drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
0219             str_yes_no(dram_info->symmetric_memory));
0220
0221     return 0;
0222 }
0223
0224 static enum intel_dram_type
0225 skl_get_dram_type(struct drm_i915_private *i915)
0226 {
0227     u32 val;
0228
0229     val = intel_uncore_read(&i915->uncore,
0230                 SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
0231
0232     switch (val & SKL_DRAM_DDR_TYPE_MASK) {
0233     case SKL_DRAM_DDR_TYPE_DDR3:
0234         return INTEL_DRAM_DDR3;
0235     case SKL_DRAM_DDR_TYPE_DDR4:
0236         return INTEL_DRAM_DDR4;
0237     case SKL_DRAM_DDR_TYPE_LPDDR3:
0238         return INTEL_DRAM_LPDDR3;
0239     case SKL_DRAM_DDR_TYPE_LPDDR4:
0240         return INTEL_DRAM_LPDDR4;
0241     default:
0242         MISSING_CASE(val);
0243         return INTEL_DRAM_UNKNOWN;
0244     }
0245 }
0246
0247 static int
0248 skl_get_dram_info(struct drm_i915_private *i915)
0249 {
0250     struct dram_info *dram_info = &i915->dram_info;
0251     int ret;
0252
0253     dram_info->type = skl_get_dram_type(i915);
0254     drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
0255             intel_dram_type_str(dram_info->type));
0256
0257     ret = skl_dram_get_channels_info(i915);
0258     if (ret)
0259         return ret;
0260
0261     return 0;
0262 }
0263
0264 /* Returns Gb per DRAM device */
0265 static int bxt_get_dimm_size(u32 val)
0266 {
0267     switch (val & BXT_DRAM_SIZE_MASK) {
0268     case BXT_DRAM_SIZE_4GBIT:
0269         return 4;
0270     case BXT_DRAM_SIZE_6GBIT:
0271         return 6;
0272     case BXT_DRAM_SIZE_8GBIT:
0273         return 8;
0274     case BXT_DRAM_SIZE_12GBIT:
0275         return 12;
0276     case BXT_DRAM_SIZE_16GBIT:
0277         return 16;
0278     default:
0279         MISSING_CASE(val);
0280         return 0;
0281     }
0282 }
0283
0284 static int bxt_get_dimm_width(u32 val)
0285 {
0286     if (!bxt_get_dimm_size(val))
0287         return 0;
0288
0289     val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
0290
0291     return 8 << val;
0292 }
0293
0294 static int bxt_get_dimm_ranks(u32 val)
0295 {
0296     if (!bxt_get_dimm_size(val))
0297         return 0;
0298
0299     switch (val & BXT_DRAM_RANK_MASK) {
0300     case BXT_DRAM_RANK_SINGLE:
0301         return 1;
0302     case BXT_DRAM_RANK_DUAL:
0303         return 2;
0304     default:
0305         MISSING_CASE(val);
0306         return 0;
0307     }
0308 }
0309
0310 static enum intel_dram_type bxt_get_dimm_type(u32 val)
0311 {
0312     if (!bxt_get_dimm_size(val))
0313         return INTEL_DRAM_UNKNOWN;
0314
0315     switch (val & BXT_DRAM_TYPE_MASK) {
0316     case BXT_DRAM_TYPE_DDR3:
0317         return INTEL_DRAM_DDR3;
0318     case BXT_DRAM_TYPE_LPDDR3:
0319         return INTEL_DRAM_LPDDR3;
0320     case BXT_DRAM_TYPE_DDR4:
0321         return INTEL_DRAM_DDR4;
0322     case BXT_DRAM_TYPE_LPDDR4:
0323         return INTEL_DRAM_LPDDR4;
0324     default:
0325         MISSING_CASE(val);
0326         return INTEL_DRAM_UNKNOWN;
0327     }
0328 }
0329
0330 static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
0331 {
0332     dimm->width = bxt_get_dimm_width(val);
0333     dimm->ranks = bxt_get_dimm_ranks(val);
0334
0335     /*
0336      * Size in register is Gb per DRAM device. Convert to total
0337      * Gb to match the way we report this for non-LP platforms.
0338      */
0339     dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm);
0340 }
0341
0342 static int bxt_get_dram_info(struct drm_i915_private *i915)
0343 {
0344     struct dram_info *dram_info = &i915->dram_info;
0345     u32 val;
0346     u8 valid_ranks = 0;
0347     int i;
0348
0349     /*
0350      * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
0351      */
0352     for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
0353         struct dram_dimm_info dimm;
0354         enum intel_dram_type type;
0355
0356         val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
0357         if (val == 0xFFFFFFFF)
0358             continue;
0359
0360         dram_info->num_channels++;
0361
0362         bxt_get_dimm_info(&dimm, val);
0363         type = bxt_get_dimm_type(val);
0364
0365         drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&
0366                 dram_info->type != INTEL_DRAM_UNKNOWN &&
0367                 dram_info->type != type);
0368
0369         drm_dbg_kms(&i915->drm,
0370                 "CH%u DIMM size: %u Gb, width: X%u, ranks: %u, type: %s\n",
0371                 i - BXT_D_CR_DRP0_DUNIT_START,
0372                 dimm.size, dimm.width, dimm.ranks,
0373                 intel_dram_type_str(type));
0374
0375         if (valid_ranks == 0)
0376             valid_ranks = dimm.ranks;
0377
0378         if (type != INTEL_DRAM_UNKNOWN)
0379             dram_info->type = type;
0380     }
0381
0382     if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
0383         drm_info(&i915->drm, "couldn't get memory information\n");
0384         return -EINVAL;
0385     }
0386
0387     return 0;
0388 }
0389
0390 static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
0391 {
0392     struct dram_info *dram_info = &dev_priv->dram_info;
0393     u32 val = 0;
0394     int ret;
0395
0396     ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
0397                  ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
0398     if (ret)
0399         return ret;
0400
0401     if (GRAPHICS_VER(dev_priv) == 12) {
0402         switch (val & 0xf) {
0403         case 0:
0404             dram_info->type = INTEL_DRAM_DDR4;
0405             break;
0406         case 1:
0407             dram_info->type = INTEL_DRAM_DDR5;
0408             break;
0409         case 2:
0410             dram_info->type = INTEL_DRAM_LPDDR5;
0411             break;
0412         case 3:
0413             dram_info->type = INTEL_DRAM_LPDDR4;
0414             break;
0415         case 4:
0416             dram_info->type = INTEL_DRAM_DDR3;
0417             break;
0418         case 5:
0419             dram_info->type = INTEL_DRAM_LPDDR3;
0420             break;
0421         default:
0422             MISSING_CASE(val & 0xf);
0423             return -EINVAL;
0424         }
0425     } else {
0426         switch (val & 0xf) {
0427         case 0:
0428             dram_info->type = INTEL_DRAM_DDR4;
0429             break;
0430         case 1:
0431             dram_info->type = INTEL_DRAM_DDR3;
0432             break;
0433         case 2:
0434             dram_info->type = INTEL_DRAM_LPDDR3;
0435             break;
0436         case 3:
0437             dram_info->type = INTEL_DRAM_LPDDR4;
0438             break;
0439         default:
0440             MISSING_CASE(val & 0xf);
0441             return -EINVAL;
0442         }
0443     }
0444
0445     dram_info->num_channels = (val & 0xf0) >> 4;
0446     dram_info->num_qgv_points = (val & 0xf00) >> 8;
0447     dram_info->num_psf_gv_points = (val & 0x3000) >> 12;
0448
0449     return 0;
0450 }
0451
0452 static int gen11_get_dram_info(struct drm_i915_private *i915)
0453 {
0454     int ret = skl_get_dram_info(i915);
0455
0456     if (ret)
0457         return ret;
0458
0459     return icl_pcode_read_mem_global_info(i915);
0460 }
0461
0462 static int gen12_get_dram_info(struct drm_i915_private *i915)
0463 {
0464     i915->dram_info.wm_lv_0_adjust_needed = false;
0465
0466     return icl_pcode_read_mem_global_info(i915);
0467 }
0468
0469 void intel_dram_detect(struct drm_i915_private *i915)
0470 {
0471     struct dram_info *dram_info = &i915->dram_info;
0472     int ret;
0473
0474     if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
0475         return;
0476
0477     /*
0478      * Assume level 0 watermark latency adjustment is needed until proven
0479      * otherwise, this w/a is not needed by bxt/glk.
0480      */
0481     dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
0482
0483     if (GRAPHICS_VER(i915) >= 12)
0484         ret = gen12_get_dram_info(i915);
0485     else if (GRAPHICS_VER(i915) >= 11)
0486         ret = gen11_get_dram_info(i915);
0487     else if (IS_GEN9_LP(i915))
0488         ret = bxt_get_dram_info(i915);
0489     else
0490         ret = skl_get_dram_info(i915);
0491     if (ret)
0492         return;
0493
0494     drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
0495
0496     drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",
0497             str_yes_no(dram_info->wm_lv_0_adjust_needed));
0498 }
0499
0500 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
0501 {
0502     static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
0503     static const u8 sets[4] = { 1, 1, 2, 2 };
0504
0505     return EDRAM_NUM_BANKS(cap) *
0506         ways[EDRAM_WAYS_IDX(cap)] *
0507         sets[EDRAM_SETS_IDX(cap)];
0508 }
0509
0510 void intel_dram_edram_detect(struct drm_i915_private *i915)
0511 {
0512     u32 edram_cap = 0;
0513
0514     if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
0515         return;
0516
0517     edram_cap = __raw_uncore_read32(&i915->uncore, HSW_EDRAM_CAP);
0518
0519     /* NB: We can't write IDICR yet because we don't have gt funcs set up */
0520
0521     if (!(edram_cap & EDRAM_ENABLED))
0522         return;
0523
0524     /*
0525      * The needed capability bits for size calculation are not there with
0526      * pre gen9 so return 128MB always.
0527      */
0528     if (GRAPHICS_VER(i915) < 9)
0529         i915->edram_size_mb = 128;
0530     else
0531         i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
0532
0533     drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);
0534 }