drm/i915/intel_device_info.h

0001 /*
0002  * Copyright © 2014-2017 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #ifndef _INTEL_DEVICE_INFO_H_
0026 #define _INTEL_DEVICE_INFO_H_
0027
0028 #include <uapi/drm/i915_drm.h>
0029
0030 #include "intel_step.h"
0031
0032 #include "display/intel_display.h"
0033
0034 #include "gt/intel_engine_types.h"
0035 #include "gt/intel_context_types.h"
0036 #include "gt/intel_sseu.h"
0037
0038 struct drm_printer;
0039 struct drm_i915_private;
0040
0041 /* Keep in gen based order, and chronological order within a gen */
0042 enum intel_platform {
0043     INTEL_PLATFORM_UNINITIALIZED = 0,
0044     /* gen2 */
0045     INTEL_I830,
0046     INTEL_I845G,
0047     INTEL_I85X,
0048     INTEL_I865G,
0049     /* gen3 */
0050     INTEL_I915G,
0051     INTEL_I915GM,
0052     INTEL_I945G,
0053     INTEL_I945GM,
0054     INTEL_G33,
0055     INTEL_PINEVIEW,
0056     /* gen4 */
0057     INTEL_I965G,
0058     INTEL_I965GM,
0059     INTEL_G45,
0060     INTEL_GM45,
0061     /* gen5 */
0062     INTEL_IRONLAKE,
0063     /* gen6 */
0064     INTEL_SANDYBRIDGE,
0065     /* gen7 */
0066     INTEL_IVYBRIDGE,
0067     INTEL_VALLEYVIEW,
0068     INTEL_HASWELL,
0069     /* gen8 */
0070     INTEL_BROADWELL,
0071     INTEL_CHERRYVIEW,
0072     /* gen9 */
0073     INTEL_SKYLAKE,
0074     INTEL_BROXTON,
0075     INTEL_KABYLAKE,
0076     INTEL_GEMINILAKE,
0077     INTEL_COFFEELAKE,
0078     INTEL_COMETLAKE,
0079     /* gen11 */
0080     INTEL_ICELAKE,
0081     INTEL_ELKHARTLAKE,
0082     INTEL_JASPERLAKE,
0083     /* gen12 */
0084     INTEL_TIGERLAKE,
0085     INTEL_ROCKETLAKE,
0086     INTEL_DG1,
0087     INTEL_ALDERLAKE_S,
0088     INTEL_ALDERLAKE_P,
0089     INTEL_XEHPSDV,
0090     INTEL_DG2,
0091     INTEL_PONTEVECCHIO,
0092     INTEL_METEORLAKE,
0093     INTEL_MAX_PLATFORMS
0094 };
0095
0096 /*
0097  * Subplatform bits share the same namespace per parent platform. In other words
0098  * it is fine for the same bit to be used on multiple parent platforms.
0099  */
0100
0101 #define INTEL_SUBPLATFORM_BITS (3)
0102 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
0103
0104 /* HSW/BDW/SKL/KBL/CFL */
0105 #define INTEL_SUBPLATFORM_ULT   (0)
0106 #define INTEL_SUBPLATFORM_ULX   (1)
0107
0108 /* ICL */
0109 #define INTEL_SUBPLATFORM_PORTF (0)
0110
0111 /* TGL */
0112 #define INTEL_SUBPLATFORM_UY    (0)
0113
0114 /* DG2 */
0115 #define INTEL_SUBPLATFORM_G10   0
0116 #define INTEL_SUBPLATFORM_G11   1
0117 #define INTEL_SUBPLATFORM_G12   2
0118
0119 /* ADL */
0120 #define INTEL_SUBPLATFORM_RPL   0
0121
0122 /* ADL-P */
0123 /*
0124  * As #define INTEL_SUBPLATFORM_RPL 0 will apply
0125  * here too, SUBPLATFORM_N will have different
0126  * bit set
0127  */
0128 #define INTEL_SUBPLATFORM_N    1
0129
0130 /* MTL */
0131 #define INTEL_SUBPLATFORM_M 0
0132 #define INTEL_SUBPLATFORM_P 1
0133
0134 enum intel_ppgtt_type {
0135     INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
0136     INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
0137     INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
0138 };
0139
0140 #define DEV_INFO_FOR_EACH_FLAG(func) \
0141     func(is_mobile); \
0142     func(is_lp); \
0143     func(require_force_probe); \
0144     func(is_dgfx); \
0145     /* Keep has_* in alphabetical order */ \
0146     func(has_64bit_reloc); \
0147     func(has_64k_pages); \
0148     func(needs_compact_pt); \
0149     func(gpu_reset_clobbers_display); \
0150     func(has_reset_engine); \
0151     func(has_3d_pipeline); \
0152     func(has_4tile); \
0153     func(has_flat_ccs); \
0154     func(has_global_mocs); \
0155     func(has_gt_uc); \
0156     func(has_heci_pxp); \
0157     func(has_heci_gscfi); \
0158     func(has_guc_deprivilege); \
0159     func(has_l3_ccs_read); \
0160     func(has_l3_dpf); \
0161     func(has_llc); \
0162     func(has_logical_ring_contexts); \
0163     func(has_logical_ring_elsq); \
0164     func(has_media_ratio_mode); \
0165     func(has_mslice_steering); \
0166     func(has_one_eu_per_fuse_bit); \
0167     func(has_pooled_eu); \
0168     func(has_pxp); \
0169     func(has_rc6); \
0170     func(has_rc6p); \
0171     func(has_rps); \
0172     func(has_runtime_pm); \
0173     func(has_snoop); \
0174     func(has_coherent_ggtt); \
0175     func(unfenced_needs_alignment); \
0176     func(hws_needs_physical);
0177
0178 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
0179     /* Keep in alphabetical order */ \
0180     func(cursor_needs_physical); \
0181     func(has_cdclk_crawl); \
0182     func(has_dmc); \
0183     func(has_ddi); \
0184     func(has_dp_mst); \
0185     func(has_dsb); \
0186     func(has_dsc); \
0187     func(has_fpga_dbg); \
0188     func(has_gmch); \
0189     func(has_hdcp); \
0190     func(has_hotplug); \
0191     func(has_hti); \
0192     func(has_ipc); \
0193     func(has_modular_fia); \
0194     func(has_overlay); \
0195     func(has_psr); \
0196     func(has_psr_hw_tracking); \
0197     func(overlay_needs_physical); \
0198     func(supports_tv);
0199
0200 struct ip_version {
0201     u8 ver;
0202     u8 rel;
0203 };
0204
0205 struct intel_device_info {
0206     struct ip_version graphics;
0207     struct ip_version media;
0208
0209     intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
0210
0211     enum intel_platform platform;
0212
0213     unsigned int dma_mask_size; /* available DMA address bits */
0214
0215     enum intel_ppgtt_type ppgtt_type;
0216     unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
0217
0218     unsigned int page_sizes; /* page sizes supported by the HW */
0219
0220     u32 memory_regions; /* regions supported by the HW */
0221
0222     u8 gt; /* GT number, 0 if undefined */
0223
0224 #define DEFINE_FLAG(name) u8 name:1
0225     DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
0226 #undef DEFINE_FLAG
0227
0228     struct {
0229         u8 ver;
0230         u8 rel;
0231
0232         u8 pipe_mask;
0233         u8 cpu_transcoder_mask;
0234         u8 fbc_mask;
0235         u8 abox_mask;
0236
0237         struct {
0238             u16 size; /* in blocks */
0239             u8 slice_mask;
0240         } dbuf;
0241
0242 #define DEFINE_FLAG(name) u8 name:1
0243         DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
0244 #undef DEFINE_FLAG
0245
0246         /* Global register offset for the display engine */
0247         u32 mmio_offset;
0248
0249         /* Register offsets for the various display pipes and transcoders */
0250         u32 pipe_offsets[I915_MAX_TRANSCODERS];
0251         u32 trans_offsets[I915_MAX_TRANSCODERS];
0252         u32 cursor_offsets[I915_MAX_PIPES];
0253
0254         struct {
0255             u32 degamma_lut_size;
0256             u32 gamma_lut_size;
0257             u32 degamma_lut_tests;
0258             u32 gamma_lut_tests;
0259         } color;
0260     } display;
0261 };
0262
0263 struct intel_runtime_info {
0264     /*
0265      * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
0266      * into single runtime conditionals, and also to provide groundwork
0267      * for future per platform, or per SKU build optimizations.
0268      *
0269      * Array can be extended when necessary if the corresponding
0270      * BUILD_BUG_ON is hit.
0271      */
0272     u32 platform_mask[2];
0273
0274     u16 device_id;
0275
0276     u8 num_sprites[I915_MAX_PIPES];
0277     u8 num_scalers[I915_MAX_PIPES];
0278
0279     u32 rawclk_freq;
0280
0281     struct intel_step_info step;
0282 };
0283
0284 struct intel_driver_caps {
0285     unsigned int scheduler;
0286     bool has_logical_contexts:1;
0287 };
0288
0289 const char *intel_platform_name(enum intel_platform platform);
0290
0291 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
0292 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
0293
0294 void intel_device_info_print_static(const struct intel_device_info *info,
0295                     struct drm_printer *p);
0296 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
0297                      struct drm_printer *p);
0298
0299 void intel_driver_caps_print(const struct intel_driver_caps *caps,
0300                  struct drm_printer *p);
0301
0302 #endif