drm/i915/intel_device_info.c

0001 /*
0002  * Copyright © 2016 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #include <linux/string_helpers.h>
0026
0027 #include <drm/drm_print.h>
0028 #include <drm/i915_pciids.h>
0029
0030 #include "display/intel_cdclk.h"
0031 #include "display/intel_de.h"
0032 #include "intel_device_info.h"
0033 #include "i915_drv.h"
0034 #include "i915_utils.h"
0035
0036 #define PLATFORM_NAME(x) [INTEL_##x] = #x
0037 static const char * const platform_names[] = {
0038     PLATFORM_NAME(I830),
0039     PLATFORM_NAME(I845G),
0040     PLATFORM_NAME(I85X),
0041     PLATFORM_NAME(I865G),
0042     PLATFORM_NAME(I915G),
0043     PLATFORM_NAME(I915GM),
0044     PLATFORM_NAME(I945G),
0045     PLATFORM_NAME(I945GM),
0046     PLATFORM_NAME(G33),
0047     PLATFORM_NAME(PINEVIEW),
0048     PLATFORM_NAME(I965G),
0049     PLATFORM_NAME(I965GM),
0050     PLATFORM_NAME(G45),
0051     PLATFORM_NAME(GM45),
0052     PLATFORM_NAME(IRONLAKE),
0053     PLATFORM_NAME(SANDYBRIDGE),
0054     PLATFORM_NAME(IVYBRIDGE),
0055     PLATFORM_NAME(VALLEYVIEW),
0056     PLATFORM_NAME(HASWELL),
0057     PLATFORM_NAME(BROADWELL),
0058     PLATFORM_NAME(CHERRYVIEW),
0059     PLATFORM_NAME(SKYLAKE),
0060     PLATFORM_NAME(BROXTON),
0061     PLATFORM_NAME(KABYLAKE),
0062     PLATFORM_NAME(GEMINILAKE),
0063     PLATFORM_NAME(COFFEELAKE),
0064     PLATFORM_NAME(COMETLAKE),
0065     PLATFORM_NAME(ICELAKE),
0066     PLATFORM_NAME(ELKHARTLAKE),
0067     PLATFORM_NAME(JASPERLAKE),
0068     PLATFORM_NAME(TIGERLAKE),
0069     PLATFORM_NAME(ROCKETLAKE),
0070     PLATFORM_NAME(DG1),
0071     PLATFORM_NAME(ALDERLAKE_S),
0072     PLATFORM_NAME(ALDERLAKE_P),
0073     PLATFORM_NAME(XEHPSDV),
0074     PLATFORM_NAME(DG2),
0075     PLATFORM_NAME(PONTEVECCHIO),
0076     PLATFORM_NAME(METEORLAKE),
0077 };
0078 #undef PLATFORM_NAME
0079
0080 const char *intel_platform_name(enum intel_platform platform)
0081 {
0082     BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
0083
0084     if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
0085              platform_names[platform] == NULL))
0086         return "<unknown>";
0087
0088     return platform_names[platform];
0089 }
0090
0091 void intel_device_info_print_static(const struct intel_device_info *info,
0092                     struct drm_printer *p)
0093 {
0094     if (info->graphics.rel)
0095         drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver,
0096                info->graphics.rel);
0097     else
0098         drm_printf(p, "graphics version: %u\n", info->graphics.ver);
0099
0100     if (info->media.rel)
0101         drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel);
0102     else
0103         drm_printf(p, "media version: %u\n", info->media.ver);
0104
0105     if (info->display.rel)
0106         drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel);
0107     else
0108         drm_printf(p, "display version: %u\n", info->display.ver);
0109
0110     drm_printf(p, "gt: %d\n", info->gt);
0111     drm_printf(p, "memory-regions: %x\n", info->memory_regions);
0112     drm_printf(p, "page-sizes: %x\n", info->page_sizes);
0113     drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
0114     drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
0115     drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
0116     drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
0117
0118 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
0119     DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
0120 #undef PRINT_FLAG
0121
0122 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
0123     DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
0124 #undef PRINT_FLAG
0125 }
0126
0127 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
0128                      struct drm_printer *p)
0129 {
0130     drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
0131 }
0132
0133 #undef INTEL_VGA_DEVICE
0134 #define INTEL_VGA_DEVICE(id, info) (id)
0135
0136 static const u16 subplatform_ult_ids[] = {
0137     INTEL_HSW_ULT_GT1_IDS(0),
0138     INTEL_HSW_ULT_GT2_IDS(0),
0139     INTEL_HSW_ULT_GT3_IDS(0),
0140     INTEL_BDW_ULT_GT1_IDS(0),
0141     INTEL_BDW_ULT_GT2_IDS(0),
0142     INTEL_BDW_ULT_GT3_IDS(0),
0143     INTEL_BDW_ULT_RSVD_IDS(0),
0144     INTEL_SKL_ULT_GT1_IDS(0),
0145     INTEL_SKL_ULT_GT2_IDS(0),
0146     INTEL_SKL_ULT_GT3_IDS(0),
0147     INTEL_KBL_ULT_GT1_IDS(0),
0148     INTEL_KBL_ULT_GT2_IDS(0),
0149     INTEL_KBL_ULT_GT3_IDS(0),
0150     INTEL_CFL_U_GT2_IDS(0),
0151     INTEL_CFL_U_GT3_IDS(0),
0152     INTEL_WHL_U_GT1_IDS(0),
0153     INTEL_WHL_U_GT2_IDS(0),
0154     INTEL_WHL_U_GT3_IDS(0),
0155     INTEL_CML_U_GT1_IDS(0),
0156     INTEL_CML_U_GT2_IDS(0),
0157 };
0158
0159 static const u16 subplatform_ulx_ids[] = {
0160     INTEL_HSW_ULX_GT1_IDS(0),
0161     INTEL_HSW_ULX_GT2_IDS(0),
0162     INTEL_BDW_ULX_GT1_IDS(0),
0163     INTEL_BDW_ULX_GT2_IDS(0),
0164     INTEL_BDW_ULX_GT3_IDS(0),
0165     INTEL_BDW_ULX_RSVD_IDS(0),
0166     INTEL_SKL_ULX_GT1_IDS(0),
0167     INTEL_SKL_ULX_GT2_IDS(0),
0168     INTEL_KBL_ULX_GT1_IDS(0),
0169     INTEL_KBL_ULX_GT2_IDS(0),
0170     INTEL_AML_KBL_GT2_IDS(0),
0171     INTEL_AML_CFL_GT2_IDS(0),
0172 };
0173
0174 static const u16 subplatform_portf_ids[] = {
0175     INTEL_ICL_PORT_F_IDS(0),
0176 };
0177
0178 static const u16 subplatform_uy_ids[] = {
0179     INTEL_TGL_12_GT2_IDS(0),
0180 };
0181
0182 static const u16 subplatform_n_ids[] = {
0183     INTEL_ADLN_IDS(0),
0184 };
0185
0186 static const u16 subplatform_rpl_ids[] = {
0187     INTEL_RPLS_IDS(0),
0188     INTEL_RPLP_IDS(0),
0189 };
0190
0191 static const u16 subplatform_g10_ids[] = {
0192     INTEL_DG2_G10_IDS(0),
0193     INTEL_ATS_M150_IDS(0),
0194 };
0195
0196 static const u16 subplatform_g11_ids[] = {
0197     INTEL_DG2_G11_IDS(0),
0198     INTEL_ATS_M75_IDS(0),
0199 };
0200
0201 static const u16 subplatform_g12_ids[] = {
0202     INTEL_DG2_G12_IDS(0),
0203 };
0204
0205 static const u16 subplatform_m_ids[] = {
0206     INTEL_MTL_M_IDS(0),
0207 };
0208
0209 static const u16 subplatform_p_ids[] = {
0210     INTEL_MTL_P_IDS(0),
0211 };
0212
0213 static bool find_devid(u16 id, const u16 *p, unsigned int num)
0214 {
0215     for (; num; num--, p++) {
0216         if (*p == id)
0217             return true;
0218     }
0219
0220     return false;
0221 }
0222
0223 void intel_device_info_subplatform_init(struct drm_i915_private *i915)
0224 {
0225     const struct intel_device_info *info = INTEL_INFO(i915);
0226     const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
0227     const unsigned int pi = __platform_mask_index(rinfo, info->platform);
0228     const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
0229     u16 devid = INTEL_DEVID(i915);
0230     u32 mask = 0;
0231
0232     /* Make sure IS_<platform> checks are working. */
0233     RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
0234
0235     /* Find and mark subplatform bits based on the PCI device id. */
0236     if (find_devid(devid, subplatform_ult_ids,
0237                ARRAY_SIZE(subplatform_ult_ids))) {
0238         mask = BIT(INTEL_SUBPLATFORM_ULT);
0239     } else if (find_devid(devid, subplatform_ulx_ids,
0240                   ARRAY_SIZE(subplatform_ulx_ids))) {
0241         mask = BIT(INTEL_SUBPLATFORM_ULX);
0242         if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
0243             /* ULX machines are also considered ULT. */
0244             mask |= BIT(INTEL_SUBPLATFORM_ULT);
0245         }
0246     } else if (find_devid(devid, subplatform_portf_ids,
0247                   ARRAY_SIZE(subplatform_portf_ids))) {
0248         mask = BIT(INTEL_SUBPLATFORM_PORTF);
0249     } else if (find_devid(devid, subplatform_uy_ids,
0250                ARRAY_SIZE(subplatform_uy_ids))) {
0251         mask = BIT(INTEL_SUBPLATFORM_UY);
0252     } else if (find_devid(devid, subplatform_n_ids,
0253                 ARRAY_SIZE(subplatform_n_ids))) {
0254         mask = BIT(INTEL_SUBPLATFORM_N);
0255     } else if (find_devid(devid, subplatform_rpl_ids,
0256                   ARRAY_SIZE(subplatform_rpl_ids))) {
0257         mask = BIT(INTEL_SUBPLATFORM_RPL);
0258     } else if (find_devid(devid, subplatform_g10_ids,
0259                   ARRAY_SIZE(subplatform_g10_ids))) {
0260         mask = BIT(INTEL_SUBPLATFORM_G10);
0261     } else if (find_devid(devid, subplatform_g11_ids,
0262                   ARRAY_SIZE(subplatform_g11_ids))) {
0263         mask = BIT(INTEL_SUBPLATFORM_G11);
0264     } else if (find_devid(devid, subplatform_g12_ids,
0265                   ARRAY_SIZE(subplatform_g12_ids))) {
0266         mask = BIT(INTEL_SUBPLATFORM_G12);
0267     } else if (find_devid(devid, subplatform_m_ids,
0268                   ARRAY_SIZE(subplatform_m_ids))) {
0269         mask = BIT(INTEL_SUBPLATFORM_M);
0270     } else if (find_devid(devid, subplatform_p_ids,
0271                   ARRAY_SIZE(subplatform_p_ids))) {
0272         mask = BIT(INTEL_SUBPLATFORM_P);
0273     }
0274
0275     GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
0276
0277     RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
0278 }
0279
0280 /**
0281  * intel_device_info_runtime_init - initialize runtime info
0282  * @dev_priv: the i915 device
0283  *
0284  * Determine various intel_device_info fields at runtime.
0285  *
0286  * Use it when either:
0287  *   - it's judged too laborious to fill n static structures with the limit
0288  *     when a simple if statement does the job,
0289  *   - run-time checks (eg read fuse/strap registers) are needed.
0290  *
0291  * This function needs to be called:
0292  *   - after the MMIO has been setup as we are reading registers,
0293  *   - after the PCH has been detected,
0294  *   - before the first usage of the fields it can tweak.
0295  */
0296 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
0297 {
0298     struct intel_device_info *info = mkwrite_device_info(dev_priv);
0299     struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
0300     enum pipe pipe;
0301
0302     /* Wa_14011765242: adl-s A0,A1 */
0303     if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
0304         for_each_pipe(dev_priv, pipe)
0305             runtime->num_scalers[pipe] = 0;
0306     else if (DISPLAY_VER(dev_priv) >= 11) {
0307         for_each_pipe(dev_priv, pipe)
0308             runtime->num_scalers[pipe] = 2;
0309     } else if (DISPLAY_VER(dev_priv) >= 9) {
0310         runtime->num_scalers[PIPE_A] = 2;
0311         runtime->num_scalers[PIPE_B] = 2;
0312         runtime->num_scalers[PIPE_C] = 1;
0313     }
0314
0315     BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
0316
0317     if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
0318         for_each_pipe(dev_priv, pipe)
0319             runtime->num_sprites[pipe] = 4;
0320     else if (DISPLAY_VER(dev_priv) >= 11)
0321         for_each_pipe(dev_priv, pipe)
0322             runtime->num_sprites[pipe] = 6;
0323     else if (DISPLAY_VER(dev_priv) == 10)
0324         for_each_pipe(dev_priv, pipe)
0325             runtime->num_sprites[pipe] = 3;
0326     else if (IS_BROXTON(dev_priv)) {
0327         /*
0328          * Skylake and Broxton currently don't expose the topmost plane as its
0329          * use is exclusive with the legacy cursor and we only want to expose
0330          * one of those, not both. Until we can safely expose the topmost plane
0331          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
0332          * we don't expose the topmost plane at all to prevent ABI breakage
0333          * down the line.
0334          */
0335
0336         runtime->num_sprites[PIPE_A] = 2;
0337         runtime->num_sprites[PIPE_B] = 2;
0338         runtime->num_sprites[PIPE_C] = 1;
0339     } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
0340         for_each_pipe(dev_priv, pipe)
0341             runtime->num_sprites[pipe] = 2;
0342     } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
0343         for_each_pipe(dev_priv, pipe)
0344             runtime->num_sprites[pipe] = 1;
0345     }
0346
0347     if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
0348         HAS_PCH_SPLIT(dev_priv)) {
0349         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
0350         u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
0351
0352         /*
0353          * SFUSE_STRAP is supposed to have a bit signalling the display
0354          * is fused off. Unfortunately it seems that, at least in
0355          * certain cases, fused off display means that PCH display
0356          * reads don't land anywhere. In that case, we read 0s.
0357          *
0358          * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
0359          * should be set when taking over after the firmware.
0360          */
0361         if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
0362             sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
0363             (HAS_PCH_CPT(dev_priv) &&
0364              !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
0365             drm_info(&dev_priv->drm,
0366                  "Display fused off, disabling\n");
0367             info->display.pipe_mask = 0;
0368             info->display.cpu_transcoder_mask = 0;
0369             info->display.fbc_mask = 0;
0370         } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
0371             drm_info(&dev_priv->drm, "PipeC fused off\n");
0372             info->display.pipe_mask &= ~BIT(PIPE_C);
0373             info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
0374         }
0375     } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
0376         u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
0377
0378         if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
0379             info->display.pipe_mask &= ~BIT(PIPE_A);
0380             info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
0381             info->display.fbc_mask &= ~BIT(INTEL_FBC_A);
0382         }
0383         if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
0384             info->display.pipe_mask &= ~BIT(PIPE_B);
0385             info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
0386         }
0387         if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
0388             info->display.pipe_mask &= ~BIT(PIPE_C);
0389             info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
0390         }
0391
0392         if (DISPLAY_VER(dev_priv) >= 12 &&
0393             (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
0394             info->display.pipe_mask &= ~BIT(PIPE_D);
0395             info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
0396         }
0397
0398         if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
0399             info->display.has_hdcp = 0;
0400
0401         if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
0402             info->display.fbc_mask = 0;
0403
0404         if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
0405             info->display.has_dmc = 0;
0406
0407         if (DISPLAY_VER(dev_priv) >= 10 &&
0408             (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
0409             info->display.has_dsc = 0;
0410     }
0411
0412     if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
0413         drm_info(&dev_priv->drm,
0414              "Disabling ppGTT for VT-d support\n");
0415         info->ppgtt_type = INTEL_PPGTT_NONE;
0416     }
0417
0418     runtime->rawclk_freq = intel_read_rawclk(dev_priv);
0419     drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
0420
0421     if (!HAS_DISPLAY(dev_priv)) {
0422         dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
0423                            DRIVER_ATOMIC);
0424         memset(&info->display, 0, sizeof(info->display));
0425         memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
0426         memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
0427     }
0428 }
0429
0430 void intel_driver_caps_print(const struct intel_driver_caps *caps,
0431                  struct drm_printer *p)
0432 {
0433     drm_printf(p, "Has logical contexts? %s\n",
0434            str_yes_no(caps->has_logical_contexts));
0435     drm_printf(p, "scheduler: %x\n", caps->scheduler);
0436 }