drm/i915/i915_reg_defs.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005
0006 #ifndef __I915_REG_DEFS__
0007 #define __I915_REG_DEFS__
0008
0009 #include <linux/bitfield.h>
0010 #include <linux/bits.h>
0011
0012 /**
0013  * REG_BIT() - Prepare a u32 bit value
0014  * @__n: 0-based bit number
0015  *
0016  * Local wrapper for BIT() to force u32, with compile time checks.
0017  *
0018  * @return: Value with bit @__n set.
0019  */
0020 #define REG_BIT(__n)                            \
0021     ((u32)(BIT(__n) +                       \
0022            BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&     \
0023                  ((__n) < 0 || (__n) > 31))))
0024
0025 /**
0026  * REG_GENMASK() - Prepare a continuous u32 bitmask
0027  * @__high: 0-based high bit
0028  * @__low: 0-based low bit
0029  *
0030  * Local wrapper for GENMASK() to force u32, with compile time checks.
0031  *
0032  * @return: Continuous bitmask from @__high to @__low, inclusive.
0033  */
0034 #define REG_GENMASK(__high, __low)                  \
0035     ((u32)(GENMASK(__high, __low) +                 \
0036            BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&  \
0037                  __is_constexpr(__low) &&       \
0038                  ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
0039
0040 /**
0041  * REG_GENMASK64() - Prepare a continuous u64 bitmask
0042  * @__high: 0-based high bit
0043  * @__low: 0-based low bit
0044  *
0045  * Local wrapper for GENMASK_ULL() to force u64, with compile time checks.
0046  *
0047  * @return: Continuous bitmask from @__high to @__low, inclusive.
0048  */
0049 #define REG_GENMASK64(__high, __low)                    \
0050     ((u64)(GENMASK_ULL(__high, __low) +             \
0051            BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&      \
0052                  __is_constexpr(__low) &&       \
0053                  ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
0054
0055 /*
0056  * Local integer constant expression version of is_power_of_2().
0057  */
0058 #define IS_POWER_OF_2(__x)      ((__x) && (((__x) & ((__x) - 1)) == 0))
0059
0060 /**
0061  * REG_FIELD_PREP() - Prepare a u32 bitfield value
0062  * @__mask: shifted mask defining the field's length and position
0063  * @__val: value to put in the field
0064  *
0065  * Local copy of FIELD_PREP() to generate an integer constant expression, force
0066  * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
0067  *
0068  * @return: @__val masked and shifted into the field defined by @__mask.
0069  */
0070 #define REG_FIELD_PREP(__mask, __val)                       \
0071     ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
0072            BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +     \
0073            BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +     \
0074            BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
0075            BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
0076
0077 /**
0078  * REG_FIELD_GET() - Extract a u32 bitfield value
0079  * @__mask: shifted mask defining the field's length and position
0080  * @__val: value to extract the bitfield value from
0081  *
0082  * Local wrapper for FIELD_GET() to force u32 and for consistency with
0083  * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
0084  *
0085  * @return: Masked and shifted value of the field defined by @__mask in @__val.
0086  */
0087 #define REG_FIELD_GET(__mask, __val)    ((u32)FIELD_GET(__mask, __val))
0088
0089 /**
0090  * REG_FIELD_GET64() - Extract a u64 bitfield value
0091  * @__mask: shifted mask defining the field's length and position
0092  * @__val: value to extract the bitfield value from
0093  *
0094  * Local wrapper for FIELD_GET() to force u64 and for consistency with
0095  * REG_GENMASK64().
0096  *
0097  * @return: Masked and shifted value of the field defined by @__mask in @__val.
0098  */
0099 #define REG_FIELD_GET64(__mask, __val)  ((u64)FIELD_GET(__mask, __val))
0100
0101 typedef struct {
0102     u32 reg;
0103 } i915_reg_t;
0104
0105 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
0106
0107 #define INVALID_MMIO_REG _MMIO(0)
0108
0109 static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
0110 {
0111     return reg.reg;
0112 }
0113
0114 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
0115 {
0116     return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
0117 }
0118
0119 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
0120 {
0121     return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
0122 }
0123
0124 #define VLV_DISPLAY_BASE        0x180000
0125
0126 #endif /* __I915_REG_DEFS__ */