drm/i915/i915_pvinfo.h

0001 /*
0002  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0020  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0021  * SOFTWARE.
0022  */
0023
0024 #ifndef _I915_PVINFO_H_
0025 #define _I915_PVINFO_H_
0026
0027 #include <linux/types.h>
0028
0029 /* The MMIO offset of the shared info between guest and host emulator */
0030 #define VGT_PVINFO_PAGE 0x78000
0031 #define VGT_PVINFO_SIZE 0x1000
0032
0033 /*
0034  * The following structure pages are defined in GEN MMIO space
0035  * for virtualization. (One page for now)
0036  */
0037 #define VGT_MAGIC         0x4776544776544776ULL /* 'vGTvGTvG' */
0038 #define VGT_VERSION_MAJOR 1
0039 #define VGT_VERSION_MINOR 0
0040
0041 /*
0042  * notifications from guest to vgpu device model
0043  */
0044 enum vgt_g2v_type {
0045     VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
0046     VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
0047     VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
0048     VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
0049     VGT_G2V_EXECLIST_CONTEXT_CREATE,
0050     VGT_G2V_EXECLIST_CONTEXT_DESTROY,
0051     VGT_G2V_MAX,
0052 };
0053
0054 /*
0055  * VGT capabilities type
0056  */
0057 #define VGT_CAPS_FULL_PPGTT     BIT(2)
0058 #define VGT_CAPS_HWSP_EMULATION     BIT(3)
0059 #define VGT_CAPS_HUGE_GTT       BIT(4)
0060
0061 struct vgt_if {
0062     u64 magic;      /* VGT_MAGIC */
0063     u16 version_major;
0064     u16 version_minor;
0065     u32 vgt_id;     /* ID of vGT instance */
0066     u32 vgt_caps;       /* VGT capabilities */
0067     u32 rsv1[11];       /* pad to offset 0x40 */
0068     /*
0069      *  Data structure to describe the balooning info of resources.
0070      *  Each VM can only have one portion of continuous area for now.
0071      *  (May support scattered resource in future)
0072      *  (starting from offset 0x40)
0073      */
0074     struct {
0075         /* Aperture register balooning */
0076         struct {
0077             u32 base;
0078             u32 size;
0079         } mappable_gmadr;   /* aperture */
0080         /* GMADR register balooning */
0081         struct {
0082             u32 base;
0083             u32 size;
0084         } nonmappable_gmadr;    /* non aperture */
0085         /* allowed fence registers */
0086         u32 fence_num;
0087         u32 rsv2[3];
0088     } avail_rs;     /* available/assigned resource */
0089     u32 rsv3[0x200 - 24];   /* pad to half page */
0090     /*
0091      * The bottom half page is for response from Gfx driver to hypervisor.
0092      */
0093     u32 rsv4;
0094     u32 display_ready;  /* ready for display owner switch */
0095
0096     u32 rsv5[4];
0097
0098     u32 g2v_notify;
0099     u32 rsv6[5];
0100
0101     u32 cursor_x_hot;
0102     u32 cursor_y_hot;
0103
0104     struct {
0105         u32 lo;
0106         u32 hi;
0107     } pdp[4];
0108
0109     u32 execlist_context_descriptor_lo;
0110     u32 execlist_context_descriptor_hi;
0111
0112     u32  rsv7[0x200 - 24];    /* pad to one page */
0113 } __packed;
0114
0115 #define vgtif_offset(x) (offsetof(struct vgt_if, x))
0116
0117 #define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x))
0118
0119 /* vGPU display status to be used by the host side */
0120 #define VGT_DRV_DISPLAY_NOT_READY 0
0121 #define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */
0122
0123 #endif /* _I915_PVINFO_H_ */