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0001 /*
0002  * Copyright © 2016 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  *
0023  */
0024 
0025 #include <drm/drm_color_mgmt.h>
0026 #include <drm/drm_drv.h>
0027 #include <drm/i915_pciids.h>
0028 
0029 #include "i915_driver.h"
0030 #include "i915_drv.h"
0031 #include "i915_pci.h"
0032 #include "i915_reg.h"
0033 
0034 #define PLATFORM(x) .platform = (x)
0035 #define GEN(x) \
0036     .graphics.ver = (x), \
0037     .media.ver = (x), \
0038     .display.ver = (x)
0039 
0040 #define I845_PIPE_OFFSETS \
0041     .display.pipe_offsets = { \
0042         [TRANSCODER_A] = PIPE_A_OFFSET, \
0043     }, \
0044     .display.trans_offsets = { \
0045         [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
0046     }
0047 
0048 #define I9XX_PIPE_OFFSETS \
0049     .display.pipe_offsets = { \
0050         [TRANSCODER_A] = PIPE_A_OFFSET, \
0051         [TRANSCODER_B] = PIPE_B_OFFSET, \
0052     }, \
0053     .display.trans_offsets = { \
0054         [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
0055         [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
0056     }
0057 
0058 #define IVB_PIPE_OFFSETS \
0059     .display.pipe_offsets = { \
0060         [TRANSCODER_A] = PIPE_A_OFFSET, \
0061         [TRANSCODER_B] = PIPE_B_OFFSET, \
0062         [TRANSCODER_C] = PIPE_C_OFFSET, \
0063     }, \
0064     .display.trans_offsets = { \
0065         [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
0066         [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
0067         [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
0068     }
0069 
0070 #define HSW_PIPE_OFFSETS \
0071     .display.pipe_offsets = { \
0072         [TRANSCODER_A] = PIPE_A_OFFSET, \
0073         [TRANSCODER_B] = PIPE_B_OFFSET, \
0074         [TRANSCODER_C] = PIPE_C_OFFSET, \
0075         [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
0076     }, \
0077     .display.trans_offsets = { \
0078         [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
0079         [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
0080         [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
0081         [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
0082     }
0083 
0084 #define CHV_PIPE_OFFSETS \
0085     .display.pipe_offsets = { \
0086         [TRANSCODER_A] = PIPE_A_OFFSET, \
0087         [TRANSCODER_B] = PIPE_B_OFFSET, \
0088         [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
0089     }, \
0090     .display.trans_offsets = { \
0091         [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
0092         [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
0093         [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
0094     }
0095 
0096 #define I845_CURSOR_OFFSETS \
0097     .display.cursor_offsets = { \
0098         [PIPE_A] = CURSOR_A_OFFSET, \
0099     }
0100 
0101 #define I9XX_CURSOR_OFFSETS \
0102     .display.cursor_offsets = { \
0103         [PIPE_A] = CURSOR_A_OFFSET, \
0104         [PIPE_B] = CURSOR_B_OFFSET, \
0105     }
0106 
0107 #define CHV_CURSOR_OFFSETS \
0108     .display.cursor_offsets = { \
0109         [PIPE_A] = CURSOR_A_OFFSET, \
0110         [PIPE_B] = CURSOR_B_OFFSET, \
0111         [PIPE_C] = CHV_CURSOR_C_OFFSET, \
0112     }
0113 
0114 #define IVB_CURSOR_OFFSETS \
0115     .display.cursor_offsets = { \
0116         [PIPE_A] = CURSOR_A_OFFSET, \
0117         [PIPE_B] = IVB_CURSOR_B_OFFSET, \
0118         [PIPE_C] = IVB_CURSOR_C_OFFSET, \
0119     }
0120 
0121 #define TGL_CURSOR_OFFSETS \
0122     .display.cursor_offsets = { \
0123         [PIPE_A] = CURSOR_A_OFFSET, \
0124         [PIPE_B] = IVB_CURSOR_B_OFFSET, \
0125         [PIPE_C] = IVB_CURSOR_C_OFFSET, \
0126         [PIPE_D] = TGL_CURSOR_D_OFFSET, \
0127     }
0128 
0129 #define I9XX_COLORS \
0130     .display.color = { .gamma_lut_size = 256 }
0131 #define I965_COLORS \
0132     .display.color = { .gamma_lut_size = 129, \
0133            .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
0134     }
0135 #define ILK_COLORS \
0136     .display.color = { .gamma_lut_size = 1024 }
0137 #define IVB_COLORS \
0138     .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
0139 #define CHV_COLORS \
0140     .display.color = { \
0141         .degamma_lut_size = 65, .gamma_lut_size = 257, \
0142         .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
0143         .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
0144     }
0145 #define GLK_COLORS \
0146     .display.color = { \
0147         .degamma_lut_size = 33, .gamma_lut_size = 1024, \
0148         .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
0149                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
0150     }
0151 #define ICL_COLORS \
0152     .display.color = { \
0153         .degamma_lut_size = 33, .gamma_lut_size = 262145, \
0154         .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
0155                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
0156         .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
0157     }
0158 
0159 /* Keep in gen based order, and chronological order within a gen */
0160 
0161 #define GEN_DEFAULT_PAGE_SIZES \
0162     .page_sizes = I915_GTT_PAGE_SIZE_4K
0163 
0164 #define GEN_DEFAULT_REGIONS \
0165     .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
0166 
0167 #define I830_FEATURES \
0168     GEN(2), \
0169     .is_mobile = 1, \
0170     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
0171     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
0172     .display.has_overlay = 1, \
0173     .display.cursor_needs_physical = 1, \
0174     .display.overlay_needs_physical = 1, \
0175     .display.has_gmch = 1, \
0176     .gpu_reset_clobbers_display = true, \
0177     .has_3d_pipeline = 1, \
0178     .hws_needs_physical = 1, \
0179     .unfenced_needs_alignment = 1, \
0180     .platform_engine_mask = BIT(RCS0), \
0181     .has_snoop = true, \
0182     .has_coherent_ggtt = false, \
0183     .dma_mask_size = 32, \
0184     I9XX_PIPE_OFFSETS, \
0185     I9XX_CURSOR_OFFSETS, \
0186     I9XX_COLORS, \
0187     GEN_DEFAULT_PAGE_SIZES, \
0188     GEN_DEFAULT_REGIONS
0189 
0190 #define I845_FEATURES \
0191     GEN(2), \
0192     .display.pipe_mask = BIT(PIPE_A), \
0193     .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
0194     .display.has_overlay = 1, \
0195     .display.overlay_needs_physical = 1, \
0196     .display.has_gmch = 1, \
0197     .has_3d_pipeline = 1, \
0198     .gpu_reset_clobbers_display = true, \
0199     .hws_needs_physical = 1, \
0200     .unfenced_needs_alignment = 1, \
0201     .platform_engine_mask = BIT(RCS0), \
0202     .has_snoop = true, \
0203     .has_coherent_ggtt = false, \
0204     .dma_mask_size = 32, \
0205     I845_PIPE_OFFSETS, \
0206     I845_CURSOR_OFFSETS, \
0207     I9XX_COLORS, \
0208     GEN_DEFAULT_PAGE_SIZES, \
0209     GEN_DEFAULT_REGIONS
0210 
0211 static const struct intel_device_info i830_info = {
0212     I830_FEATURES,
0213     PLATFORM(INTEL_I830),
0214 };
0215 
0216 static const struct intel_device_info i845g_info = {
0217     I845_FEATURES,
0218     PLATFORM(INTEL_I845G),
0219 };
0220 
0221 static const struct intel_device_info i85x_info = {
0222     I830_FEATURES,
0223     PLATFORM(INTEL_I85X),
0224     .display.fbc_mask = BIT(INTEL_FBC_A),
0225 };
0226 
0227 static const struct intel_device_info i865g_info = {
0228     I845_FEATURES,
0229     PLATFORM(INTEL_I865G),
0230     .display.fbc_mask = BIT(INTEL_FBC_A),
0231 };
0232 
0233 #define GEN3_FEATURES \
0234     GEN(3), \
0235     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
0236     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
0237     .display.has_gmch = 1, \
0238     .gpu_reset_clobbers_display = true, \
0239     .platform_engine_mask = BIT(RCS0), \
0240     .has_3d_pipeline = 1, \
0241     .has_snoop = true, \
0242     .has_coherent_ggtt = true, \
0243     .dma_mask_size = 32, \
0244     I9XX_PIPE_OFFSETS, \
0245     I9XX_CURSOR_OFFSETS, \
0246     I9XX_COLORS, \
0247     GEN_DEFAULT_PAGE_SIZES, \
0248     GEN_DEFAULT_REGIONS
0249 
0250 static const struct intel_device_info i915g_info = {
0251     GEN3_FEATURES,
0252     PLATFORM(INTEL_I915G),
0253     .has_coherent_ggtt = false,
0254     .display.cursor_needs_physical = 1,
0255     .display.has_overlay = 1,
0256     .display.overlay_needs_physical = 1,
0257     .hws_needs_physical = 1,
0258     .unfenced_needs_alignment = 1,
0259 };
0260 
0261 static const struct intel_device_info i915gm_info = {
0262     GEN3_FEATURES,
0263     PLATFORM(INTEL_I915GM),
0264     .is_mobile = 1,
0265     .display.cursor_needs_physical = 1,
0266     .display.has_overlay = 1,
0267     .display.overlay_needs_physical = 1,
0268     .display.supports_tv = 1,
0269     .display.fbc_mask = BIT(INTEL_FBC_A),
0270     .hws_needs_physical = 1,
0271     .unfenced_needs_alignment = 1,
0272 };
0273 
0274 static const struct intel_device_info i945g_info = {
0275     GEN3_FEATURES,
0276     PLATFORM(INTEL_I945G),
0277     .display.has_hotplug = 1,
0278     .display.cursor_needs_physical = 1,
0279     .display.has_overlay = 1,
0280     .display.overlay_needs_physical = 1,
0281     .hws_needs_physical = 1,
0282     .unfenced_needs_alignment = 1,
0283 };
0284 
0285 static const struct intel_device_info i945gm_info = {
0286     GEN3_FEATURES,
0287     PLATFORM(INTEL_I945GM),
0288     .is_mobile = 1,
0289     .display.has_hotplug = 1,
0290     .display.cursor_needs_physical = 1,
0291     .display.has_overlay = 1,
0292     .display.overlay_needs_physical = 1,
0293     .display.supports_tv = 1,
0294     .display.fbc_mask = BIT(INTEL_FBC_A),
0295     .hws_needs_physical = 1,
0296     .unfenced_needs_alignment = 1,
0297 };
0298 
0299 static const struct intel_device_info g33_info = {
0300     GEN3_FEATURES,
0301     PLATFORM(INTEL_G33),
0302     .display.has_hotplug = 1,
0303     .display.has_overlay = 1,
0304     .dma_mask_size = 36,
0305 };
0306 
0307 static const struct intel_device_info pnv_g_info = {
0308     GEN3_FEATURES,
0309     PLATFORM(INTEL_PINEVIEW),
0310     .display.has_hotplug = 1,
0311     .display.has_overlay = 1,
0312     .dma_mask_size = 36,
0313 };
0314 
0315 static const struct intel_device_info pnv_m_info = {
0316     GEN3_FEATURES,
0317     PLATFORM(INTEL_PINEVIEW),
0318     .is_mobile = 1,
0319     .display.has_hotplug = 1,
0320     .display.has_overlay = 1,
0321     .dma_mask_size = 36,
0322 };
0323 
0324 #define GEN4_FEATURES \
0325     GEN(4), \
0326     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
0327     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
0328     .display.has_hotplug = 1, \
0329     .display.has_gmch = 1, \
0330     .gpu_reset_clobbers_display = true, \
0331     .platform_engine_mask = BIT(RCS0), \
0332     .has_3d_pipeline = 1, \
0333     .has_snoop = true, \
0334     .has_coherent_ggtt = true, \
0335     .dma_mask_size = 36, \
0336     I9XX_PIPE_OFFSETS, \
0337     I9XX_CURSOR_OFFSETS, \
0338     I965_COLORS, \
0339     GEN_DEFAULT_PAGE_SIZES, \
0340     GEN_DEFAULT_REGIONS
0341 
0342 static const struct intel_device_info i965g_info = {
0343     GEN4_FEATURES,
0344     PLATFORM(INTEL_I965G),
0345     .display.has_overlay = 1,
0346     .hws_needs_physical = 1,
0347     .has_snoop = false,
0348 };
0349 
0350 static const struct intel_device_info i965gm_info = {
0351     GEN4_FEATURES,
0352     PLATFORM(INTEL_I965GM),
0353     .is_mobile = 1,
0354     .display.fbc_mask = BIT(INTEL_FBC_A),
0355     .display.has_overlay = 1,
0356     .display.supports_tv = 1,
0357     .hws_needs_physical = 1,
0358     .has_snoop = false,
0359 };
0360 
0361 static const struct intel_device_info g45_info = {
0362     GEN4_FEATURES,
0363     PLATFORM(INTEL_G45),
0364     .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
0365     .gpu_reset_clobbers_display = false,
0366 };
0367 
0368 static const struct intel_device_info gm45_info = {
0369     GEN4_FEATURES,
0370     PLATFORM(INTEL_GM45),
0371     .is_mobile = 1,
0372     .display.fbc_mask = BIT(INTEL_FBC_A),
0373     .display.supports_tv = 1,
0374     .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
0375     .gpu_reset_clobbers_display = false,
0376 };
0377 
0378 #define GEN5_FEATURES \
0379     GEN(5), \
0380     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
0381     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
0382     .display.has_hotplug = 1, \
0383     .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
0384     .has_3d_pipeline = 1, \
0385     .has_snoop = true, \
0386     .has_coherent_ggtt = true, \
0387     /* ilk does support rc6, but we do not implement [power] contexts */ \
0388     .has_rc6 = 0, \
0389     .dma_mask_size = 36, \
0390     I9XX_PIPE_OFFSETS, \
0391     I9XX_CURSOR_OFFSETS, \
0392     ILK_COLORS, \
0393     GEN_DEFAULT_PAGE_SIZES, \
0394     GEN_DEFAULT_REGIONS
0395 
0396 static const struct intel_device_info ilk_d_info = {
0397     GEN5_FEATURES,
0398     PLATFORM(INTEL_IRONLAKE),
0399 };
0400 
0401 static const struct intel_device_info ilk_m_info = {
0402     GEN5_FEATURES,
0403     PLATFORM(INTEL_IRONLAKE),
0404     .is_mobile = 1,
0405     .has_rps = true,
0406     .display.fbc_mask = BIT(INTEL_FBC_A),
0407 };
0408 
0409 #define GEN6_FEATURES \
0410     GEN(6), \
0411     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
0412     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
0413     .display.has_hotplug = 1, \
0414     .display.fbc_mask = BIT(INTEL_FBC_A), \
0415     .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
0416     .has_3d_pipeline = 1, \
0417     .has_coherent_ggtt = true, \
0418     .has_llc = 1, \
0419     .has_rc6 = 1, \
0420     .has_rc6p = 1, \
0421     .has_rps = true, \
0422     .dma_mask_size = 40, \
0423     .ppgtt_type = INTEL_PPGTT_ALIASING, \
0424     .ppgtt_size = 31, \
0425     I9XX_PIPE_OFFSETS, \
0426     I9XX_CURSOR_OFFSETS, \
0427     ILK_COLORS, \
0428     GEN_DEFAULT_PAGE_SIZES, \
0429     GEN_DEFAULT_REGIONS
0430 
0431 #define SNB_D_PLATFORM \
0432     GEN6_FEATURES, \
0433     PLATFORM(INTEL_SANDYBRIDGE)
0434 
0435 static const struct intel_device_info snb_d_gt1_info = {
0436     SNB_D_PLATFORM,
0437     .gt = 1,
0438 };
0439 
0440 static const struct intel_device_info snb_d_gt2_info = {
0441     SNB_D_PLATFORM,
0442     .gt = 2,
0443 };
0444 
0445 #define SNB_M_PLATFORM \
0446     GEN6_FEATURES, \
0447     PLATFORM(INTEL_SANDYBRIDGE), \
0448     .is_mobile = 1
0449 
0450 
0451 static const struct intel_device_info snb_m_gt1_info = {
0452     SNB_M_PLATFORM,
0453     .gt = 1,
0454 };
0455 
0456 static const struct intel_device_info snb_m_gt2_info = {
0457     SNB_M_PLATFORM,
0458     .gt = 2,
0459 };
0460 
0461 #define GEN7_FEATURES  \
0462     GEN(7), \
0463     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
0464     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
0465     .display.has_hotplug = 1, \
0466     .display.fbc_mask = BIT(INTEL_FBC_A), \
0467     .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
0468     .has_3d_pipeline = 1, \
0469     .has_coherent_ggtt = true, \
0470     .has_llc = 1, \
0471     .has_rc6 = 1, \
0472     .has_rc6p = 1, \
0473     .has_reset_engine = true, \
0474     .has_rps = true, \
0475     .dma_mask_size = 40, \
0476     .ppgtt_type = INTEL_PPGTT_ALIASING, \
0477     .ppgtt_size = 31, \
0478     IVB_PIPE_OFFSETS, \
0479     IVB_CURSOR_OFFSETS, \
0480     IVB_COLORS, \
0481     GEN_DEFAULT_PAGE_SIZES, \
0482     GEN_DEFAULT_REGIONS
0483 
0484 #define IVB_D_PLATFORM \
0485     GEN7_FEATURES, \
0486     PLATFORM(INTEL_IVYBRIDGE), \
0487     .has_l3_dpf = 1
0488 
0489 static const struct intel_device_info ivb_d_gt1_info = {
0490     IVB_D_PLATFORM,
0491     .gt = 1,
0492 };
0493 
0494 static const struct intel_device_info ivb_d_gt2_info = {
0495     IVB_D_PLATFORM,
0496     .gt = 2,
0497 };
0498 
0499 #define IVB_M_PLATFORM \
0500     GEN7_FEATURES, \
0501     PLATFORM(INTEL_IVYBRIDGE), \
0502     .is_mobile = 1, \
0503     .has_l3_dpf = 1
0504 
0505 static const struct intel_device_info ivb_m_gt1_info = {
0506     IVB_M_PLATFORM,
0507     .gt = 1,
0508 };
0509 
0510 static const struct intel_device_info ivb_m_gt2_info = {
0511     IVB_M_PLATFORM,
0512     .gt = 2,
0513 };
0514 
0515 static const struct intel_device_info ivb_q_info = {
0516     GEN7_FEATURES,
0517     PLATFORM(INTEL_IVYBRIDGE),
0518     .gt = 2,
0519     .display.pipe_mask = 0, /* legal, last one wins */
0520     .display.cpu_transcoder_mask = 0,
0521     .has_l3_dpf = 1,
0522 };
0523 
0524 static const struct intel_device_info vlv_info = {
0525     PLATFORM(INTEL_VALLEYVIEW),
0526     GEN(7),
0527     .is_lp = 1,
0528     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
0529     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
0530     .has_runtime_pm = 1,
0531     .has_rc6 = 1,
0532     .has_reset_engine = true,
0533     .has_rps = true,
0534     .display.has_gmch = 1,
0535     .display.has_hotplug = 1,
0536     .dma_mask_size = 40,
0537     .ppgtt_type = INTEL_PPGTT_ALIASING,
0538     .ppgtt_size = 31,
0539     .has_snoop = true,
0540     .has_coherent_ggtt = false,
0541     .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
0542     .display.mmio_offset = VLV_DISPLAY_BASE,
0543     I9XX_PIPE_OFFSETS,
0544     I9XX_CURSOR_OFFSETS,
0545     I965_COLORS,
0546     GEN_DEFAULT_PAGE_SIZES,
0547     GEN_DEFAULT_REGIONS,
0548 };
0549 
0550 #define G75_FEATURES  \
0551     GEN7_FEATURES, \
0552     .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
0553     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
0554         BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
0555     .display.has_ddi = 1, \
0556     .display.has_fpga_dbg = 1, \
0557     .display.has_dp_mst = 1, \
0558     .has_rc6p = 0 /* RC6p removed-by HSW */, \
0559     HSW_PIPE_OFFSETS, \
0560     .has_runtime_pm = 1
0561 
0562 #define HSW_PLATFORM \
0563     G75_FEATURES, \
0564     PLATFORM(INTEL_HASWELL), \
0565     .has_l3_dpf = 1
0566 
0567 static const struct intel_device_info hsw_gt1_info = {
0568     HSW_PLATFORM,
0569     .gt = 1,
0570 };
0571 
0572 static const struct intel_device_info hsw_gt2_info = {
0573     HSW_PLATFORM,
0574     .gt = 2,
0575 };
0576 
0577 static const struct intel_device_info hsw_gt3_info = {
0578     HSW_PLATFORM,
0579     .gt = 3,
0580 };
0581 
0582 #define GEN8_FEATURES \
0583     G75_FEATURES, \
0584     GEN(8), \
0585     .has_logical_ring_contexts = 1, \
0586     .dma_mask_size = 39, \
0587     .ppgtt_type = INTEL_PPGTT_FULL, \
0588     .ppgtt_size = 48, \
0589     .has_64bit_reloc = 1
0590 
0591 #define BDW_PLATFORM \
0592     GEN8_FEATURES, \
0593     PLATFORM(INTEL_BROADWELL)
0594 
0595 static const struct intel_device_info bdw_gt1_info = {
0596     BDW_PLATFORM,
0597     .gt = 1,
0598 };
0599 
0600 static const struct intel_device_info bdw_gt2_info = {
0601     BDW_PLATFORM,
0602     .gt = 2,
0603 };
0604 
0605 static const struct intel_device_info bdw_rsvd_info = {
0606     BDW_PLATFORM,
0607     .gt = 3,
0608     /* According to the device ID those devices are GT3, they were
0609      * previously treated as not GT3, keep it like that.
0610      */
0611 };
0612 
0613 static const struct intel_device_info bdw_gt3_info = {
0614     BDW_PLATFORM,
0615     .gt = 3,
0616     .platform_engine_mask =
0617         BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
0618 };
0619 
0620 static const struct intel_device_info chv_info = {
0621     PLATFORM(INTEL_CHERRYVIEW),
0622     GEN(8),
0623     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
0624     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
0625     .display.has_hotplug = 1,
0626     .is_lp = 1,
0627     .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
0628     .has_64bit_reloc = 1,
0629     .has_runtime_pm = 1,
0630     .has_rc6 = 1,
0631     .has_rps = true,
0632     .has_logical_ring_contexts = 1,
0633     .display.has_gmch = 1,
0634     .dma_mask_size = 39,
0635     .ppgtt_type = INTEL_PPGTT_FULL,
0636     .ppgtt_size = 32,
0637     .has_reset_engine = 1,
0638     .has_snoop = true,
0639     .has_coherent_ggtt = false,
0640     .display.mmio_offset = VLV_DISPLAY_BASE,
0641     CHV_PIPE_OFFSETS,
0642     CHV_CURSOR_OFFSETS,
0643     CHV_COLORS,
0644     GEN_DEFAULT_PAGE_SIZES,
0645     GEN_DEFAULT_REGIONS,
0646 };
0647 
0648 #define GEN9_DEFAULT_PAGE_SIZES \
0649     .page_sizes = I915_GTT_PAGE_SIZE_4K | \
0650               I915_GTT_PAGE_SIZE_64K
0651 
0652 #define GEN9_FEATURES \
0653     GEN8_FEATURES, \
0654     GEN(9), \
0655     GEN9_DEFAULT_PAGE_SIZES, \
0656     .display.has_dmc = 1, \
0657     .has_gt_uc = 1, \
0658     .display.has_hdcp = 1, \
0659     .display.has_ipc = 1, \
0660     .display.has_psr = 1, \
0661     .display.has_psr_hw_tracking = 1, \
0662     .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
0663     .display.dbuf.slice_mask = BIT(DBUF_S1)
0664 
0665 #define SKL_PLATFORM \
0666     GEN9_FEATURES, \
0667     PLATFORM(INTEL_SKYLAKE)
0668 
0669 static const struct intel_device_info skl_gt1_info = {
0670     SKL_PLATFORM,
0671     .gt = 1,
0672 };
0673 
0674 static const struct intel_device_info skl_gt2_info = {
0675     SKL_PLATFORM,
0676     .gt = 2,
0677 };
0678 
0679 #define SKL_GT3_PLUS_PLATFORM \
0680     SKL_PLATFORM, \
0681     .platform_engine_mask = \
0682         BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
0683 
0684 
0685 static const struct intel_device_info skl_gt3_info = {
0686     SKL_GT3_PLUS_PLATFORM,
0687     .gt = 3,
0688 };
0689 
0690 static const struct intel_device_info skl_gt4_info = {
0691     SKL_GT3_PLUS_PLATFORM,
0692     .gt = 4,
0693 };
0694 
0695 #define GEN9_LP_FEATURES \
0696     GEN(9), \
0697     .is_lp = 1, \
0698     .display.dbuf.slice_mask = BIT(DBUF_S1), \
0699     .display.has_hotplug = 1, \
0700     .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
0701     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
0702     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
0703         BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
0704         BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
0705     .has_3d_pipeline = 1, \
0706     .has_64bit_reloc = 1, \
0707     .display.has_ddi = 1, \
0708     .display.has_fpga_dbg = 1, \
0709     .display.fbc_mask = BIT(INTEL_FBC_A), \
0710     .display.has_hdcp = 1, \
0711     .display.has_psr = 1, \
0712     .display.has_psr_hw_tracking = 1, \
0713     .has_runtime_pm = 1, \
0714     .display.has_dmc = 1, \
0715     .has_rc6 = 1, \
0716     .has_rps = true, \
0717     .display.has_dp_mst = 1, \
0718     .has_logical_ring_contexts = 1, \
0719     .has_gt_uc = 1, \
0720     .dma_mask_size = 39, \
0721     .ppgtt_type = INTEL_PPGTT_FULL, \
0722     .ppgtt_size = 48, \
0723     .has_reset_engine = 1, \
0724     .has_snoop = true, \
0725     .has_coherent_ggtt = false, \
0726     .display.has_ipc = 1, \
0727     HSW_PIPE_OFFSETS, \
0728     IVB_CURSOR_OFFSETS, \
0729     IVB_COLORS, \
0730     GEN9_DEFAULT_PAGE_SIZES, \
0731     GEN_DEFAULT_REGIONS
0732 
0733 static const struct intel_device_info bxt_info = {
0734     GEN9_LP_FEATURES,
0735     PLATFORM(INTEL_BROXTON),
0736     .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
0737 };
0738 
0739 static const struct intel_device_info glk_info = {
0740     GEN9_LP_FEATURES,
0741     PLATFORM(INTEL_GEMINILAKE),
0742     .display.ver = 10,
0743     .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
0744     GLK_COLORS,
0745 };
0746 
0747 #define KBL_PLATFORM \
0748     GEN9_FEATURES, \
0749     PLATFORM(INTEL_KABYLAKE)
0750 
0751 static const struct intel_device_info kbl_gt1_info = {
0752     KBL_PLATFORM,
0753     .gt = 1,
0754 };
0755 
0756 static const struct intel_device_info kbl_gt2_info = {
0757     KBL_PLATFORM,
0758     .gt = 2,
0759 };
0760 
0761 static const struct intel_device_info kbl_gt3_info = {
0762     KBL_PLATFORM,
0763     .gt = 3,
0764     .platform_engine_mask =
0765         BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
0766 };
0767 
0768 #define CFL_PLATFORM \
0769     GEN9_FEATURES, \
0770     PLATFORM(INTEL_COFFEELAKE)
0771 
0772 static const struct intel_device_info cfl_gt1_info = {
0773     CFL_PLATFORM,
0774     .gt = 1,
0775 };
0776 
0777 static const struct intel_device_info cfl_gt2_info = {
0778     CFL_PLATFORM,
0779     .gt = 2,
0780 };
0781 
0782 static const struct intel_device_info cfl_gt3_info = {
0783     CFL_PLATFORM,
0784     .gt = 3,
0785     .platform_engine_mask =
0786         BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
0787 };
0788 
0789 #define CML_PLATFORM \
0790     GEN9_FEATURES, \
0791     PLATFORM(INTEL_COMETLAKE)
0792 
0793 static const struct intel_device_info cml_gt1_info = {
0794     CML_PLATFORM,
0795     .gt = 1,
0796 };
0797 
0798 static const struct intel_device_info cml_gt2_info = {
0799     CML_PLATFORM,
0800     .gt = 2,
0801 };
0802 
0803 #define GEN11_DEFAULT_PAGE_SIZES \
0804     .page_sizes = I915_GTT_PAGE_SIZE_4K | \
0805               I915_GTT_PAGE_SIZE_64K | \
0806               I915_GTT_PAGE_SIZE_2M
0807 
0808 #define GEN11_FEATURES \
0809     GEN9_FEATURES, \
0810     GEN11_DEFAULT_PAGE_SIZES, \
0811     .display.abox_mask = BIT(0), \
0812     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
0813         BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
0814         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
0815     .display.pipe_offsets = { \
0816         [TRANSCODER_A] = PIPE_A_OFFSET, \
0817         [TRANSCODER_B] = PIPE_B_OFFSET, \
0818         [TRANSCODER_C] = PIPE_C_OFFSET, \
0819         [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
0820         [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
0821         [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
0822     }, \
0823     .display.trans_offsets = { \
0824         [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
0825         [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
0826         [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
0827         [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
0828         [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
0829         [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
0830     }, \
0831     GEN(11), \
0832     ICL_COLORS, \
0833     .display.dbuf.size = 2048, \
0834     .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
0835     .display.has_dsc = 1, \
0836     .has_coherent_ggtt = false, \
0837     .has_logical_ring_elsq = 1
0838 
0839 static const struct intel_device_info icl_info = {
0840     GEN11_FEATURES,
0841     PLATFORM(INTEL_ICELAKE),
0842     .platform_engine_mask =
0843         BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
0844 };
0845 
0846 static const struct intel_device_info ehl_info = {
0847     GEN11_FEATURES,
0848     PLATFORM(INTEL_ELKHARTLAKE),
0849     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
0850     .ppgtt_size = 36,
0851 };
0852 
0853 static const struct intel_device_info jsl_info = {
0854     GEN11_FEATURES,
0855     PLATFORM(INTEL_JASPERLAKE),
0856     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
0857     .ppgtt_size = 36,
0858 };
0859 
0860 #define GEN12_FEATURES \
0861     GEN11_FEATURES, \
0862     GEN(12), \
0863     .display.abox_mask = GENMASK(2, 1), \
0864     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
0865     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
0866         BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
0867         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
0868     .display.pipe_offsets = { \
0869         [TRANSCODER_A] = PIPE_A_OFFSET, \
0870         [TRANSCODER_B] = PIPE_B_OFFSET, \
0871         [TRANSCODER_C] = PIPE_C_OFFSET, \
0872         [TRANSCODER_D] = PIPE_D_OFFSET, \
0873         [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
0874         [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
0875     }, \
0876     .display.trans_offsets = { \
0877         [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
0878         [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
0879         [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
0880         [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
0881         [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
0882         [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
0883     }, \
0884     TGL_CURSOR_OFFSETS, \
0885     .has_global_mocs = 1, \
0886     .has_pxp = 1, \
0887     .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
0888 
0889 static const struct intel_device_info tgl_info = {
0890     GEN12_FEATURES,
0891     PLATFORM(INTEL_TIGERLAKE),
0892     .display.has_modular_fia = 1,
0893     .platform_engine_mask =
0894         BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
0895 };
0896 
0897 static const struct intel_device_info rkl_info = {
0898     GEN12_FEATURES,
0899     PLATFORM(INTEL_ROCKETLAKE),
0900     .display.abox_mask = BIT(0),
0901     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
0902     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
0903         BIT(TRANSCODER_C),
0904     .display.has_hti = 1,
0905     .display.has_psr_hw_tracking = 0,
0906     .platform_engine_mask =
0907         BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
0908 };
0909 
0910 #define DGFX_FEATURES \
0911     .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
0912     .has_llc = 0, \
0913     .has_pxp = 0, \
0914     .has_snoop = 1, \
0915     .is_dgfx = 1, \
0916     .has_heci_gscfi = 1
0917 
0918 static const struct intel_device_info dg1_info = {
0919     GEN12_FEATURES,
0920     DGFX_FEATURES,
0921     .graphics.rel = 10,
0922     PLATFORM(INTEL_DG1),
0923     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
0924     .require_force_probe = 1,
0925     .platform_engine_mask =
0926         BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
0927         BIT(VCS0) | BIT(VCS2),
0928     /* Wa_16011227922 */
0929     .ppgtt_size = 47,
0930 };
0931 
0932 static const struct intel_device_info adl_s_info = {
0933     GEN12_FEATURES,
0934     PLATFORM(INTEL_ALDERLAKE_S),
0935     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
0936     .display.has_hti = 1,
0937     .display.has_psr_hw_tracking = 0,
0938     .platform_engine_mask =
0939         BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
0940     .dma_mask_size = 39,
0941 };
0942 
0943 #define XE_LPD_FEATURES \
0944     .display.abox_mask = GENMASK(1, 0),                 \
0945     .display.color = {                          \
0946         .degamma_lut_size = 128, .gamma_lut_size = 1024,        \
0947         .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |     \
0948                      DRM_COLOR_LUT_EQUAL_CHANNELS,      \
0949     },                                  \
0950     .display.dbuf.size = 4096,                      \
0951     .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
0952         BIT(DBUF_S4),                           \
0953     .display.has_ddi = 1,                           \
0954     .display.has_dmc = 1,                           \
0955     .display.has_dp_mst = 1,                        \
0956     .display.has_dsb = 1,                           \
0957     .display.has_dsc = 1,                           \
0958     .display.fbc_mask = BIT(INTEL_FBC_A),                   \
0959     .display.has_fpga_dbg = 1,                      \
0960     .display.has_hdcp = 1,                          \
0961     .display.has_hotplug = 1,                       \
0962     .display.has_ipc = 1,                           \
0963     .display.has_psr = 1,                           \
0964     .display.ver = 13,                          \
0965     .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
0966     .display.pipe_offsets = {                       \
0967         [TRANSCODER_A] = PIPE_A_OFFSET,                 \
0968         [TRANSCODER_B] = PIPE_B_OFFSET,                 \
0969         [TRANSCODER_C] = PIPE_C_OFFSET,                 \
0970         [TRANSCODER_D] = PIPE_D_OFFSET,                 \
0971         [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,              \
0972         [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,              \
0973     },                                  \
0974     .display.trans_offsets = {                      \
0975         [TRANSCODER_A] = TRANSCODER_A_OFFSET,               \
0976         [TRANSCODER_B] = TRANSCODER_B_OFFSET,               \
0977         [TRANSCODER_C] = TRANSCODER_C_OFFSET,               \
0978         [TRANSCODER_D] = TRANSCODER_D_OFFSET,               \
0979         [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,            \
0980         [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,            \
0981     },                                  \
0982     TGL_CURSOR_OFFSETS
0983 
0984 static const struct intel_device_info adl_p_info = {
0985     GEN12_FEATURES,
0986     XE_LPD_FEATURES,
0987     PLATFORM(INTEL_ALDERLAKE_P),
0988     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
0989                    BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
0990                    BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
0991     .display.has_cdclk_crawl = 1,
0992     .display.has_modular_fia = 1,
0993     .display.has_psr_hw_tracking = 0,
0994     .platform_engine_mask =
0995         BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
0996     .ppgtt_size = 48,
0997     .dma_mask_size = 39,
0998 };
0999 
1000 #undef GEN
1001 
1002 #define XE_HP_PAGE_SIZES \
1003     .page_sizes = I915_GTT_PAGE_SIZE_4K | \
1004               I915_GTT_PAGE_SIZE_64K | \
1005               I915_GTT_PAGE_SIZE_2M
1006 
1007 #define XE_HP_FEATURES \
1008     .graphics.ver = 12, \
1009     .graphics.rel = 50, \
1010     XE_HP_PAGE_SIZES, \
1011     .dma_mask_size = 46, \
1012     .has_3d_pipeline = 1, \
1013     .has_64bit_reloc = 1, \
1014     .has_flat_ccs = 1, \
1015     .has_global_mocs = 1, \
1016     .has_gt_uc = 1, \
1017     .has_llc = 1, \
1018     .has_logical_ring_contexts = 1, \
1019     .has_logical_ring_elsq = 1, \
1020     .has_mslice_steering = 1, \
1021     .has_rc6 = 1, \
1022     .has_reset_engine = 1, \
1023     .has_rps = 1, \
1024     .has_runtime_pm = 1, \
1025     .ppgtt_size = 48, \
1026     .ppgtt_type = INTEL_PPGTT_FULL
1027 
1028 #define XE_HPM_FEATURES \
1029     .media.ver = 12, \
1030     .media.rel = 50
1031 
1032 __maybe_unused
1033 static const struct intel_device_info xehpsdv_info = {
1034     XE_HP_FEATURES,
1035     XE_HPM_FEATURES,
1036     DGFX_FEATURES,
1037     PLATFORM(INTEL_XEHPSDV),
1038     .display = { },
1039     .has_64k_pages = 1,
1040     .needs_compact_pt = 1,
1041     .has_media_ratio_mode = 1,
1042     .platform_engine_mask =
1043         BIT(RCS0) | BIT(BCS0) |
1044         BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1045         BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1046         BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
1047         BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1048     .require_force_probe = 1,
1049 };
1050 
1051 #define DG2_FEATURES \
1052     XE_HP_FEATURES, \
1053     XE_HPM_FEATURES, \
1054     DGFX_FEATURES, \
1055     .graphics.rel = 55, \
1056     .media.rel = 55, \
1057     PLATFORM(INTEL_DG2), \
1058     .has_4tile = 1, \
1059     .has_64k_pages = 1, \
1060     .has_guc_deprivilege = 1, \
1061     .has_heci_pxp = 1, \
1062     .needs_compact_pt = 1, \
1063     .has_media_ratio_mode = 1, \
1064     .platform_engine_mask = \
1065         BIT(RCS0) | BIT(BCS0) | \
1066         BIT(VECS0) | BIT(VECS1) | \
1067         BIT(VCS0) | BIT(VCS2) | \
1068         BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
1069 
1070 static const struct intel_device_info dg2_info = {
1071     DG2_FEATURES,
1072     XE_LPD_FEATURES,
1073     .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1074                    BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1075     .require_force_probe = 1,
1076 };
1077 
1078 static const struct intel_device_info ats_m_info = {
1079     DG2_FEATURES,
1080     .display = { 0 },
1081     .require_force_probe = 1,
1082 };
1083 
1084 #define XE_HPC_FEATURES \
1085     XE_HP_FEATURES, \
1086     .dma_mask_size = 52, \
1087     .has_3d_pipeline = 0, \
1088     .has_guc_deprivilege = 1, \
1089     .has_l3_ccs_read = 1, \
1090     .has_mslice_steering = 0, \
1091     .has_one_eu_per_fuse_bit = 1
1092 
1093 __maybe_unused
1094 static const struct intel_device_info pvc_info = {
1095     XE_HPC_FEATURES,
1096     XE_HPM_FEATURES,
1097     DGFX_FEATURES,
1098     .graphics.rel = 60,
1099     .media.rel = 60,
1100     PLATFORM(INTEL_PONTEVECCHIO),
1101     .display = { 0 },
1102     .has_flat_ccs = 0,
1103     .platform_engine_mask =
1104         BIT(BCS0) |
1105         BIT(VCS0) |
1106         BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1107     .require_force_probe = 1,
1108 };
1109 
1110 #define XE_LPDP_FEATURES    \
1111     XE_LPD_FEATURES,    \
1112     .display.ver = 14,  \
1113     .display.has_cdclk_crawl = 1
1114 
1115 __maybe_unused
1116 static const struct intel_device_info mtl_info = {
1117     XE_HP_FEATURES,
1118     XE_LPDP_FEATURES,
1119     /*
1120      * Real graphics IP version will be obtained from hardware GMD_ID
1121      * register.  Value provided here is just for sanity checking.
1122      */
1123     .graphics.ver = 12,
1124     .graphics.rel = 70,
1125     .media.ver = 13,
1126     PLATFORM(INTEL_METEORLAKE),
1127     .display.has_modular_fia = 1,
1128     .has_flat_ccs = 0,
1129     .has_snoop = 1,
1130     .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
1131     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
1132     .require_force_probe = 1,
1133 };
1134 
1135 #undef PLATFORM
1136 
1137 /*
1138  * Make sure any device matches here are from most specific to most
1139  * general.  For example, since the Quanta match is based on the subsystem
1140  * and subvendor IDs, we need it to come before the more general IVB
1141  * PCI ID matches, otherwise we'll use the wrong info struct above.
1142  */
1143 static const struct pci_device_id pciidlist[] = {
1144     INTEL_I830_IDS(&i830_info),
1145     INTEL_I845G_IDS(&i845g_info),
1146     INTEL_I85X_IDS(&i85x_info),
1147     INTEL_I865G_IDS(&i865g_info),
1148     INTEL_I915G_IDS(&i915g_info),
1149     INTEL_I915GM_IDS(&i915gm_info),
1150     INTEL_I945G_IDS(&i945g_info),
1151     INTEL_I945GM_IDS(&i945gm_info),
1152     INTEL_I965G_IDS(&i965g_info),
1153     INTEL_G33_IDS(&g33_info),
1154     INTEL_I965GM_IDS(&i965gm_info),
1155     INTEL_GM45_IDS(&gm45_info),
1156     INTEL_G45_IDS(&g45_info),
1157     INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1158     INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1159     INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1160     INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1161     INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1162     INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1163     INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1164     INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1165     INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1166     INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1167     INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1168     INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1169     INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1170     INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1171     INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1172     INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1173     INTEL_VLV_IDS(&vlv_info),
1174     INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1175     INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1176     INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1177     INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1178     INTEL_CHV_IDS(&chv_info),
1179     INTEL_SKL_GT1_IDS(&skl_gt1_info),
1180     INTEL_SKL_GT2_IDS(&skl_gt2_info),
1181     INTEL_SKL_GT3_IDS(&skl_gt3_info),
1182     INTEL_SKL_GT4_IDS(&skl_gt4_info),
1183     INTEL_BXT_IDS(&bxt_info),
1184     INTEL_GLK_IDS(&glk_info),
1185     INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1186     INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1187     INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1188     INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1189     INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1190     INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1191     INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1192     INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1193     INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1194     INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1195     INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1196     INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1197     INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1198     INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1199     INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1200     INTEL_CML_GT1_IDS(&cml_gt1_info),
1201     INTEL_CML_GT2_IDS(&cml_gt2_info),
1202     INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1203     INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1204     INTEL_ICL_11_IDS(&icl_info),
1205     INTEL_EHL_IDS(&ehl_info),
1206     INTEL_JSL_IDS(&jsl_info),
1207     INTEL_TGL_12_IDS(&tgl_info),
1208     INTEL_RKL_IDS(&rkl_info),
1209     INTEL_ADLS_IDS(&adl_s_info),
1210     INTEL_ADLP_IDS(&adl_p_info),
1211     INTEL_ADLN_IDS(&adl_p_info),
1212     INTEL_DG1_IDS(&dg1_info),
1213     INTEL_RPLS_IDS(&adl_s_info),
1214     INTEL_RPLP_IDS(&adl_p_info),
1215     INTEL_DG2_IDS(&dg2_info),
1216     INTEL_ATS_M_IDS(&ats_m_info),
1217     INTEL_MTL_IDS(&mtl_info),
1218     {0, 0, 0}
1219 };
1220 MODULE_DEVICE_TABLE(pci, pciidlist);
1221 
1222 static void i915_pci_remove(struct pci_dev *pdev)
1223 {
1224     struct drm_i915_private *i915;
1225 
1226     i915 = pci_get_drvdata(pdev);
1227     if (!i915) /* driver load aborted, nothing to cleanup */
1228         return;
1229 
1230     i915_driver_remove(i915);
1231     pci_set_drvdata(pdev, NULL);
1232 }
1233 
1234 /* is device_id present in comma separated list of ids */
1235 static bool force_probe(u16 device_id, const char *devices)
1236 {
1237     char *s, *p, *tok;
1238     bool ret;
1239 
1240     if (!devices || !*devices)
1241         return false;
1242 
1243     /* match everything */
1244     if (strcmp(devices, "*") == 0)
1245         return true;
1246 
1247     s = kstrdup(devices, GFP_KERNEL);
1248     if (!s)
1249         return false;
1250 
1251     for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1252         u16 val;
1253 
1254         if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1255             ret = true;
1256             break;
1257         }
1258     }
1259 
1260     kfree(s);
1261 
1262     return ret;
1263 }
1264 
1265 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1266 {
1267     struct intel_device_info *intel_info =
1268         (struct intel_device_info *) ent->driver_data;
1269     int err;
1270 
1271     if (intel_info->require_force_probe &&
1272         !force_probe(pdev->device, i915_modparams.force_probe)) {
1273         dev_info(&pdev->dev,
1274              "Your graphics device %04x is not properly supported by the driver in this\n"
1275              "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1276              "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1277              "or (recommended) check for kernel updates.\n",
1278              pdev->device, pdev->device, pdev->device);
1279         return -ENODEV;
1280     }
1281 
1282     /* Only bind to function 0 of the device. Early generations
1283      * used function 1 as a placeholder for multi-head. This causes
1284      * us confusion instead, especially on the systems where both
1285      * functions have the same PCI-ID!
1286      */
1287     if (PCI_FUNC(pdev->devfn))
1288         return -ENODEV;
1289 
1290     /* Detect if we need to wait for other drivers early on */
1291     if (intel_modeset_probe_defer(pdev))
1292         return -EPROBE_DEFER;
1293 
1294     err = i915_driver_probe(pdev, ent);
1295     if (err)
1296         return err;
1297 
1298     if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1299         i915_pci_remove(pdev);
1300         return -ENODEV;
1301     }
1302 
1303     err = i915_live_selftests(pdev);
1304     if (err) {
1305         i915_pci_remove(pdev);
1306         return err > 0 ? -ENOTTY : err;
1307     }
1308 
1309     err = i915_perf_selftests(pdev);
1310     if (err) {
1311         i915_pci_remove(pdev);
1312         return err > 0 ? -ENOTTY : err;
1313     }
1314 
1315     return 0;
1316 }
1317 
1318 static void i915_pci_shutdown(struct pci_dev *pdev)
1319 {
1320     struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1321 
1322     i915_driver_shutdown(i915);
1323 }
1324 
1325 static struct pci_driver i915_pci_driver = {
1326     .name = DRIVER_NAME,
1327     .id_table = pciidlist,
1328     .probe = i915_pci_probe,
1329     .remove = i915_pci_remove,
1330     .shutdown = i915_pci_shutdown,
1331     .driver.pm = &i915_pm_ops,
1332 };
1333 
1334 int i915_pci_register_driver(void)
1335 {
1336     return pci_register_driver(&i915_pci_driver);
1337 }
1338 
1339 void i915_pci_unregister_driver(void)
1340 {
1341     pci_unregister_driver(&i915_pci_driver);
1342 }
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