drm/i915/i915_irq.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #ifndef __I915_IRQ_H__
0007 #define __I915_IRQ_H__
0008
0009 #include <linux/ktime.h>
0010 #include <linux/types.h>
0011
0012 #include "i915_reg.h"
0013
0014 enum pipe;
0015 struct drm_crtc;
0016 struct drm_device;
0017 struct drm_display_mode;
0018 struct drm_i915_private;
0019 struct intel_crtc;
0020 struct intel_uncore;
0021
0022 void intel_irq_init(struct drm_i915_private *dev_priv);
0023 void intel_irq_fini(struct drm_i915_private *dev_priv);
0024 int intel_irq_install(struct drm_i915_private *dev_priv);
0025 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
0026
0027 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
0028                   enum pipe pipe);
0029 void
0030 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
0031              u32 status_mask);
0032
0033 void
0034 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
0035               u32 status_mask);
0036
0037 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
0038 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
0039
0040 void intel_hpd_irq_setup(struct drm_i915_private *i915);
0041 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
0042                    u32 mask,
0043                    u32 bits);
0044
0045 void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits);
0046 void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits);
0047
0048 void bdw_enable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
0049 void bdw_disable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
0050
0051 void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits);
0052 void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits);
0053
0054 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
0055 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
0056 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
0057 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
0058 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
0059 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
0060 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
0061 u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
0062
0063 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
0064 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
0065 bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
0066 void intel_synchronize_irq(struct drm_i915_private *i915);
0067 void intel_synchronize_hardirq(struct drm_i915_private *i915);
0068
0069 int intel_get_crtc_scanline(struct intel_crtc *crtc);
0070 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
0071                      u8 pipe_mask);
0072 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
0073                      u8 pipe_mask);
0074 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv);
0075
0076 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
0077                      ktime_t *vblank_time, bool in_vblank_irq);
0078
0079 u32 i915_get_vblank_counter(struct drm_crtc *crtc);
0080 u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
0081
0082 int i8xx_enable_vblank(struct drm_crtc *crtc);
0083 int i915gm_enable_vblank(struct drm_crtc *crtc);
0084 int i965_enable_vblank(struct drm_crtc *crtc);
0085 int ilk_enable_vblank(struct drm_crtc *crtc);
0086 int bdw_enable_vblank(struct drm_crtc *crtc);
0087 void i8xx_disable_vblank(struct drm_crtc *crtc);
0088 void i915gm_disable_vblank(struct drm_crtc *crtc);
0089 void i965_disable_vblank(struct drm_crtc *crtc);
0090 void ilk_disable_vblank(struct drm_crtc *crtc);
0091 void bdw_disable_vblank(struct drm_crtc *crtc);
0092
0093 void gen2_irq_reset(struct intel_uncore *uncore);
0094 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
0095             i915_reg_t iir, i915_reg_t ier);
0096
0097 void gen2_irq_init(struct intel_uncore *uncore,
0098            u32 imr_val, u32 ier_val);
0099 void gen3_irq_init(struct intel_uncore *uncore,
0100            i915_reg_t imr, u32 imr_val,
0101            i915_reg_t ier, u32 ier_val,
0102            i915_reg_t iir);
0103
0104 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \
0105 ({ \
0106     unsigned int which_ = which; \
0107     gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
0108                GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
0109 })
0110
0111 #define GEN3_IRQ_RESET(uncore, type) \
0112     gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
0113
0114 #define GEN2_IRQ_RESET(uncore) \
0115     gen2_irq_reset(uncore)
0116
0117 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
0118 ({ \
0119     unsigned int which_ = which; \
0120     gen3_irq_init((uncore), \
0121               GEN8_##type##_IMR(which_), imr_val, \
0122               GEN8_##type##_IER(which_), ier_val, \
0123               GEN8_##type##_IIR(which_)); \
0124 })
0125
0126 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
0127     gen3_irq_init((uncore), \
0128               type##IMR, imr_val, \
0129               type##IER, ier_val, \
0130               type##IIR)
0131
0132 #define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
0133     gen2_irq_init((uncore), imr_val, ier_val)
0134
0135 #endif /* __I915_IRQ_H__ */