drm/i915/i915_ioctl.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005
0006 #include "gt/intel_engine_regs.h"
0007
0008 #include "i915_drv.h"
0009 #include "i915_gem.h"
0010 #include "i915_ioctl.h"
0011 #include "i915_reg.h"
0012 #include "intel_runtime_pm.h"
0013 #include "intel_uncore.h"
0014
0015 /*
0016  * This file is for small ioctl functions that are out of place everywhere else,
0017  * and not big enough to warrant a file of their own.
0018  *
0019  * This is not the dumping ground for random ioctls.
0020  */
0021
0022 struct reg_whitelist {
0023     i915_reg_t offset_ldw;
0024     i915_reg_t offset_udw;
0025     u8 min_graphics_ver;
0026     u8 max_graphics_ver;
0027     u8 size;
0028 };
0029
0030 static const struct reg_whitelist reg_read_whitelist[] = {
0031     {
0032         .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
0033         .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
0034         .min_graphics_ver = 4,
0035         .max_graphics_ver = 12,
0036         .size = 8
0037     }
0038 };
0039
0040 int i915_reg_read_ioctl(struct drm_device *dev,
0041             void *data, struct drm_file *unused)
0042 {
0043     struct drm_i915_private *i915 = to_i915(dev);
0044     struct intel_uncore *uncore = &i915->uncore;
0045     struct drm_i915_reg_read *reg = data;
0046     struct reg_whitelist const *entry;
0047     intel_wakeref_t wakeref;
0048     unsigned int flags;
0049     int remain;
0050     int ret = 0;
0051
0052     entry = reg_read_whitelist;
0053     remain = ARRAY_SIZE(reg_read_whitelist);
0054     while (remain) {
0055         u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
0056
0057         GEM_BUG_ON(!is_power_of_2(entry->size));
0058         GEM_BUG_ON(entry->size > 8);
0059         GEM_BUG_ON(entry_offset & (entry->size - 1));
0060
0061         if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
0062             entry_offset == (reg->offset & -entry->size))
0063             break;
0064         entry++;
0065         remain--;
0066     }
0067
0068     if (!remain)
0069         return -EINVAL;
0070
0071     flags = reg->offset & (entry->size - 1);
0072
0073     with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
0074         if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
0075             reg->val = intel_uncore_read64_2x32(uncore,
0076                                 entry->offset_ldw,
0077                                 entry->offset_udw);
0078         else if (entry->size == 8 && flags == 0)
0079             reg->val = intel_uncore_read64(uncore,
0080                                entry->offset_ldw);
0081         else if (entry->size == 4 && flags == 0)
0082             reg->val = intel_uncore_read(uncore, entry->offset_ldw);
0083         else if (entry->size == 2 && flags == 0)
0084             reg->val = intel_uncore_read16(uncore,
0085                                entry->offset_ldw);
0086         else if (entry->size == 1 && flags == 0)
0087             reg->val = intel_uncore_read8(uncore,
0088                               entry->offset_ldw);
0089         else
0090             ret = -EINVAL;
0091     }
0092
0093     return ret;
0094 }