drm/i915/i915_getparam.c

0001 /*
0002  * SPDX-License-Identifier: MIT
0003  */
0004
0005 #include "gem/i915_gem_mman.h"
0006 #include "gt/intel_engine_user.h"
0007
0008 #include "i915_cmd_parser.h"
0009 #include "i915_drv.h"
0010 #include "i915_getparam.h"
0011 #include "i915_perf.h"
0012
0013 int i915_getparam_ioctl(struct drm_device *dev, void *data,
0014             struct drm_file *file_priv)
0015 {
0016     struct drm_i915_private *i915 = to_i915(dev);
0017     struct pci_dev *pdev = to_pci_dev(dev->dev);
0018     const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
0019     drm_i915_getparam_t *param = data;
0020     int value = 0;
0021
0022     switch (param->param) {
0023     case I915_PARAM_IRQ_ACTIVE:
0024     case I915_PARAM_ALLOW_BATCHBUFFER:
0025     case I915_PARAM_LAST_DISPATCH:
0026     case I915_PARAM_HAS_EXEC_CONSTANTS:
0027         /* Reject all old ums/dri params. */
0028         return -ENODEV;
0029     case I915_PARAM_CHIPSET_ID:
0030         value = pdev->device;
0031         break;
0032     case I915_PARAM_REVISION:
0033         value = pdev->revision;
0034         break;
0035     case I915_PARAM_NUM_FENCES_AVAIL:
0036         value = to_gt(i915)->ggtt->num_fences;
0037         break;
0038     case I915_PARAM_HAS_OVERLAY:
0039         value = !!i915->overlay;
0040         break;
0041     case I915_PARAM_HAS_BSD:
0042         value = !!intel_engine_lookup_user(i915,
0043                            I915_ENGINE_CLASS_VIDEO, 0);
0044         break;
0045     case I915_PARAM_HAS_BLT:
0046         value = !!intel_engine_lookup_user(i915,
0047                            I915_ENGINE_CLASS_COPY, 0);
0048         break;
0049     case I915_PARAM_HAS_VEBOX:
0050         value = !!intel_engine_lookup_user(i915,
0051                            I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
0052         break;
0053     case I915_PARAM_HAS_BSD2:
0054         value = !!intel_engine_lookup_user(i915,
0055                            I915_ENGINE_CLASS_VIDEO, 1);
0056         break;
0057     case I915_PARAM_HAS_LLC:
0058         value = HAS_LLC(i915);
0059         break;
0060     case I915_PARAM_HAS_WT:
0061         value = HAS_WT(i915);
0062         break;
0063     case I915_PARAM_HAS_ALIASING_PPGTT:
0064         value = INTEL_PPGTT(i915);
0065         break;
0066     case I915_PARAM_HAS_SEMAPHORES:
0067         value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
0068         break;
0069     case I915_PARAM_HAS_SECURE_BATCHES:
0070         value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
0071         break;
0072     case I915_PARAM_CMD_PARSER_VERSION:
0073         value = i915_cmd_parser_get_version(i915);
0074         break;
0075     case I915_PARAM_SUBSLICE_TOTAL:
0076         value = intel_sseu_subslice_total(sseu);
0077         if (!value)
0078             return -ENODEV;
0079         break;
0080     case I915_PARAM_EU_TOTAL:
0081         value = sseu->eu_total;
0082         if (!value)
0083             return -ENODEV;
0084         break;
0085     case I915_PARAM_HAS_GPU_RESET:
0086         value = i915->params.enable_hangcheck &&
0087             intel_has_gpu_reset(to_gt(i915));
0088         if (value && intel_has_reset_engine(to_gt(i915)))
0089             value = 2;
0090         break;
0091     case I915_PARAM_HAS_RESOURCE_STREAMER:
0092         value = 0;
0093         break;
0094     case I915_PARAM_HAS_POOLED_EU:
0095         value = HAS_POOLED_EU(i915);
0096         break;
0097     case I915_PARAM_MIN_EU_IN_POOL:
0098         value = sseu->min_eu_in_pool;
0099         break;
0100     case I915_PARAM_HUC_STATUS:
0101         value = intel_huc_check_status(&to_gt(i915)->uc.huc);
0102         if (value < 0)
0103             return value;
0104         break;
0105     case I915_PARAM_MMAP_GTT_VERSION:
0106         /* Though we've started our numbering from 1, and so class all
0107          * earlier versions as 0, in effect their value is undefined as
0108          * the ioctl will report EINVAL for the unknown param!
0109          */
0110         value = i915_gem_mmap_gtt_version();
0111         break;
0112     case I915_PARAM_HAS_SCHEDULER:
0113         value = i915->caps.scheduler;
0114         break;
0115
0116     case I915_PARAM_MMAP_VERSION:
0117         /* Remember to bump this if the version changes! */
0118     case I915_PARAM_HAS_GEM:
0119     case I915_PARAM_HAS_PAGEFLIPPING:
0120     case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
0121     case I915_PARAM_HAS_RELAXED_FENCING:
0122     case I915_PARAM_HAS_COHERENT_RINGS:
0123     case I915_PARAM_HAS_RELAXED_DELTA:
0124     case I915_PARAM_HAS_GEN7_SOL_RESET:
0125     case I915_PARAM_HAS_WAIT_TIMEOUT:
0126     case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
0127     case I915_PARAM_HAS_PINNED_BATCHES:
0128     case I915_PARAM_HAS_EXEC_NO_RELOC:
0129     case I915_PARAM_HAS_EXEC_HANDLE_LUT:
0130     case I915_PARAM_HAS_COHERENT_PHYS_GTT:
0131     case I915_PARAM_HAS_EXEC_SOFTPIN:
0132     case I915_PARAM_HAS_EXEC_ASYNC:
0133     case I915_PARAM_HAS_EXEC_FENCE:
0134     case I915_PARAM_HAS_EXEC_CAPTURE:
0135     case I915_PARAM_HAS_EXEC_BATCH_FIRST:
0136     case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
0137     case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
0138     case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
0139     case I915_PARAM_HAS_USERPTR_PROBE:
0140         /* For the time being all of these are always true;
0141          * if some supported hardware does not have one of these
0142          * features this value needs to be provided from
0143          * INTEL_INFO(), a feature macro, or similar.
0144          */
0145         value = 1;
0146         break;
0147     case I915_PARAM_HAS_CONTEXT_ISOLATION:
0148         value = intel_engines_has_context_isolation(i915);
0149         break;
0150     case I915_PARAM_SLICE_MASK:
0151         /* Not supported from Xe_HP onward; use topology queries */
0152         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
0153             return -EINVAL;
0154
0155         value = sseu->slice_mask;
0156         if (!value)
0157             return -ENODEV;
0158         break;
0159     case I915_PARAM_SUBSLICE_MASK:
0160         /* Not supported from Xe_HP onward; use topology queries */
0161         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
0162             return -EINVAL;
0163
0164         /* Only copy bits from the first slice */
0165         value = intel_sseu_get_hsw_subslices(sseu, 0);
0166         if (!value)
0167             return -ENODEV;
0168         break;
0169     case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
0170         value = to_gt(i915)->clock_frequency;
0171         break;
0172     case I915_PARAM_MMAP_GTT_COHERENT:
0173         value = INTEL_INFO(i915)->has_coherent_ggtt;
0174         break;
0175     case I915_PARAM_PERF_REVISION:
0176         value = i915_perf_ioctl_version();
0177         break;
0178     default:
0179         DRM_DEBUG("Unknown parameter %d\n", param->param);
0180         return -EINVAL;
0181     }
0182
0183     if (put_user(value, param->value))
0184         return -EFAULT;
0185
0186     return 0;
0187 }