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0001 /*
0002  * Copyright © 2008 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  *
0023  * Authors:
0024  *    Eric Anholt <eric@anholt.net>
0025  *    Keith Packard <keithp@keithp.com>
0026  *
0027  */
0028 
0029 #include <linux/sched/mm.h>
0030 #include <linux/sort.h>
0031 #include <linux/string_helpers.h>
0032 
0033 #include <drm/drm_debugfs.h>
0034 
0035 #include "gem/i915_gem_context.h"
0036 #include "gt/intel_gt.h"
0037 #include "gt/intel_gt_buffer_pool.h"
0038 #include "gt/intel_gt_clock_utils.h"
0039 #include "gt/intel_gt_debugfs.h"
0040 #include "gt/intel_gt_pm.h"
0041 #include "gt/intel_gt_pm_debugfs.h"
0042 #include "gt/intel_gt_regs.h"
0043 #include "gt/intel_gt_requests.h"
0044 #include "gt/intel_rc6.h"
0045 #include "gt/intel_reset.h"
0046 #include "gt/intel_rps.h"
0047 #include "gt/intel_sseu_debugfs.h"
0048 
0049 #include "i915_debugfs.h"
0050 #include "i915_debugfs_params.h"
0051 #include "i915_driver.h"
0052 #include "i915_irq.h"
0053 #include "i915_scheduler.h"
0054 #include "intel_mchbar_regs.h"
0055 #include "intel_pm.h"
0056 
0057 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
0058 {
0059     return to_i915(node->minor->dev);
0060 }
0061 
0062 static int i915_capabilities(struct seq_file *m, void *data)
0063 {
0064     struct drm_i915_private *i915 = node_to_i915(m->private);
0065     struct drm_printer p = drm_seq_file_printer(m);
0066 
0067     seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
0068 
0069     intel_device_info_print_static(INTEL_INFO(i915), &p);
0070     intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
0071     i915_print_iommu_status(i915, &p);
0072     intel_gt_info_print(&to_gt(i915)->info, &p);
0073     intel_driver_caps_print(&i915->caps, &p);
0074 
0075     kernel_param_lock(THIS_MODULE);
0076     i915_params_dump(&i915->params, &p);
0077     kernel_param_unlock(THIS_MODULE);
0078 
0079     return 0;
0080 }
0081 
0082 static char get_tiling_flag(struct drm_i915_gem_object *obj)
0083 {
0084     switch (i915_gem_object_get_tiling(obj)) {
0085     default:
0086     case I915_TILING_NONE: return ' ';
0087     case I915_TILING_X: return 'X';
0088     case I915_TILING_Y: return 'Y';
0089     }
0090 }
0091 
0092 static char get_global_flag(struct drm_i915_gem_object *obj)
0093 {
0094     return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
0095 }
0096 
0097 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
0098 {
0099     return obj->mm.mapping ? 'M' : ' ';
0100 }
0101 
0102 static const char *
0103 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
0104 {
0105     size_t x = 0;
0106 
0107     switch (page_sizes) {
0108     case 0:
0109         return "";
0110     case I915_GTT_PAGE_SIZE_4K:
0111         return "4K";
0112     case I915_GTT_PAGE_SIZE_64K:
0113         return "64K";
0114     case I915_GTT_PAGE_SIZE_2M:
0115         return "2M";
0116     default:
0117         if (!buf)
0118             return "M";
0119 
0120         if (page_sizes & I915_GTT_PAGE_SIZE_2M)
0121             x += snprintf(buf + x, len - x, "2M, ");
0122         if (page_sizes & I915_GTT_PAGE_SIZE_64K)
0123             x += snprintf(buf + x, len - x, "64K, ");
0124         if (page_sizes & I915_GTT_PAGE_SIZE_4K)
0125             x += snprintf(buf + x, len - x, "4K, ");
0126         buf[x-2] = '\0';
0127 
0128         return buf;
0129     }
0130 }
0131 
0132 static const char *stringify_vma_type(const struct i915_vma *vma)
0133 {
0134     if (i915_vma_is_ggtt(vma))
0135         return "ggtt";
0136 
0137     if (i915_vma_is_dpt(vma))
0138         return "dpt";
0139 
0140     return "ppgtt";
0141 }
0142 
0143 static const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
0144 {
0145     switch (type) {
0146     case I915_CACHE_NONE: return " uncached";
0147     case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
0148     case I915_CACHE_L3_LLC: return " L3+LLC";
0149     case I915_CACHE_WT: return " WT";
0150     default: return "";
0151     }
0152 }
0153 
0154 void
0155 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
0156 {
0157     struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
0158     struct i915_vma *vma;
0159     int pin_count = 0;
0160 
0161     seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
0162            &obj->base,
0163            get_tiling_flag(obj),
0164            get_global_flag(obj),
0165            get_pin_mapped_flag(obj),
0166            obj->base.size / 1024,
0167            obj->read_domains,
0168            obj->write_domain,
0169            i915_cache_level_str(dev_priv, obj->cache_level),
0170            obj->mm.dirty ? " dirty" : "",
0171            obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
0172     if (obj->base.name)
0173         seq_printf(m, " (name: %d)", obj->base.name);
0174 
0175     spin_lock(&obj->vma.lock);
0176     list_for_each_entry(vma, &obj->vma.list, obj_link) {
0177         if (!drm_mm_node_allocated(&vma->node))
0178             continue;
0179 
0180         spin_unlock(&obj->vma.lock);
0181 
0182         if (i915_vma_is_pinned(vma))
0183             pin_count++;
0184 
0185         seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
0186                stringify_vma_type(vma),
0187                vma->node.start, vma->node.size,
0188                stringify_page_sizes(vma->resource->page_sizes_gtt,
0189                         NULL, 0));
0190         if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
0191             switch (vma->ggtt_view.type) {
0192             case I915_GGTT_VIEW_NORMAL:
0193                 seq_puts(m, ", normal");
0194                 break;
0195 
0196             case I915_GGTT_VIEW_PARTIAL:
0197                 seq_printf(m, ", partial [%08llx+%x]",
0198                        vma->ggtt_view.partial.offset << PAGE_SHIFT,
0199                        vma->ggtt_view.partial.size << PAGE_SHIFT);
0200                 break;
0201 
0202             case I915_GGTT_VIEW_ROTATED:
0203                 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
0204                        vma->ggtt_view.rotated.plane[0].width,
0205                        vma->ggtt_view.rotated.plane[0].height,
0206                        vma->ggtt_view.rotated.plane[0].src_stride,
0207                        vma->ggtt_view.rotated.plane[0].dst_stride,
0208                        vma->ggtt_view.rotated.plane[0].offset,
0209                        vma->ggtt_view.rotated.plane[1].width,
0210                        vma->ggtt_view.rotated.plane[1].height,
0211                        vma->ggtt_view.rotated.plane[1].src_stride,
0212                        vma->ggtt_view.rotated.plane[1].dst_stride,
0213                        vma->ggtt_view.rotated.plane[1].offset);
0214                 break;
0215 
0216             case I915_GGTT_VIEW_REMAPPED:
0217                 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
0218                        vma->ggtt_view.remapped.plane[0].width,
0219                        vma->ggtt_view.remapped.plane[0].height,
0220                        vma->ggtt_view.remapped.plane[0].src_stride,
0221                        vma->ggtt_view.remapped.plane[0].dst_stride,
0222                        vma->ggtt_view.remapped.plane[0].offset,
0223                        vma->ggtt_view.remapped.plane[1].width,
0224                        vma->ggtt_view.remapped.plane[1].height,
0225                        vma->ggtt_view.remapped.plane[1].src_stride,
0226                        vma->ggtt_view.remapped.plane[1].dst_stride,
0227                        vma->ggtt_view.remapped.plane[1].offset);
0228                 break;
0229 
0230             default:
0231                 MISSING_CASE(vma->ggtt_view.type);
0232                 break;
0233             }
0234         }
0235         if (vma->fence)
0236             seq_printf(m, " , fence: %d", vma->fence->id);
0237         seq_puts(m, ")");
0238 
0239         spin_lock(&obj->vma.lock);
0240     }
0241     spin_unlock(&obj->vma.lock);
0242 
0243     seq_printf(m, " (pinned x %d)", pin_count);
0244     if (i915_gem_object_is_stolen(obj))
0245         seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
0246     if (i915_gem_object_is_framebuffer(obj))
0247         seq_printf(m, " (fb)");
0248 }
0249 
0250 static int i915_gem_object_info(struct seq_file *m, void *data)
0251 {
0252     struct drm_i915_private *i915 = node_to_i915(m->private);
0253     struct drm_printer p = drm_seq_file_printer(m);
0254     struct intel_memory_region *mr;
0255     enum intel_region_id id;
0256 
0257     seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
0258            i915->mm.shrink_count,
0259            atomic_read(&i915->mm.free_count),
0260            i915->mm.shrink_memory);
0261     for_each_memory_region(mr, i915, id)
0262         intel_memory_region_debug(mr, &p);
0263 
0264     return 0;
0265 }
0266 
0267 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
0268 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
0269                   size_t count, loff_t *pos)
0270 {
0271     struct i915_gpu_coredump *error;
0272     ssize_t ret;
0273     void *buf;
0274 
0275     error = file->private_data;
0276     if (!error)
0277         return 0;
0278 
0279     /* Bounce buffer required because of kernfs __user API convenience. */
0280     buf = kmalloc(count, GFP_KERNEL);
0281     if (!buf)
0282         return -ENOMEM;
0283 
0284     ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);
0285     if (ret <= 0)
0286         goto out;
0287 
0288     if (!copy_to_user(ubuf, buf, ret))
0289         *pos += ret;
0290     else
0291         ret = -EFAULT;
0292 
0293 out:
0294     kfree(buf);
0295     return ret;
0296 }
0297 
0298 static int gpu_state_release(struct inode *inode, struct file *file)
0299 {
0300     i915_gpu_coredump_put(file->private_data);
0301     return 0;
0302 }
0303 
0304 static int i915_gpu_info_open(struct inode *inode, struct file *file)
0305 {
0306     struct drm_i915_private *i915 = inode->i_private;
0307     struct i915_gpu_coredump *gpu;
0308     intel_wakeref_t wakeref;
0309 
0310     gpu = NULL;
0311     with_intel_runtime_pm(&i915->runtime_pm, wakeref)
0312         gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE);
0313 
0314     if (IS_ERR(gpu))
0315         return PTR_ERR(gpu);
0316 
0317     file->private_data = gpu;
0318     return 0;
0319 }
0320 
0321 static const struct file_operations i915_gpu_info_fops = {
0322     .owner = THIS_MODULE,
0323     .open = i915_gpu_info_open,
0324     .read = gpu_state_read,
0325     .llseek = default_llseek,
0326     .release = gpu_state_release,
0327 };
0328 
0329 static ssize_t
0330 i915_error_state_write(struct file *filp,
0331                const char __user *ubuf,
0332                size_t cnt,
0333                loff_t *ppos)
0334 {
0335     struct i915_gpu_coredump *error = filp->private_data;
0336 
0337     if (!error)
0338         return 0;
0339 
0340     drm_dbg(&error->i915->drm, "Resetting error state\n");
0341     i915_reset_error_state(error->i915);
0342 
0343     return cnt;
0344 }
0345 
0346 static int i915_error_state_open(struct inode *inode, struct file *file)
0347 {
0348     struct i915_gpu_coredump *error;
0349 
0350     error = i915_first_error_state(inode->i_private);
0351     if (IS_ERR(error))
0352         return PTR_ERR(error);
0353 
0354     file->private_data  = error;
0355     return 0;
0356 }
0357 
0358 static const struct file_operations i915_error_state_fops = {
0359     .owner = THIS_MODULE,
0360     .open = i915_error_state_open,
0361     .read = gpu_state_read,
0362     .write = i915_error_state_write,
0363     .llseek = default_llseek,
0364     .release = gpu_state_release,
0365 };
0366 #endif
0367 
0368 static int i915_frequency_info(struct seq_file *m, void *unused)
0369 {
0370     struct drm_i915_private *i915 = node_to_i915(m->private);
0371     struct intel_gt *gt = to_gt(i915);
0372     struct drm_printer p = drm_seq_file_printer(m);
0373 
0374     intel_gt_pm_frequency_dump(gt, &p);
0375 
0376     return 0;
0377 }
0378 
0379 static const char *swizzle_string(unsigned swizzle)
0380 {
0381     switch (swizzle) {
0382     case I915_BIT_6_SWIZZLE_NONE:
0383         return "none";
0384     case I915_BIT_6_SWIZZLE_9:
0385         return "bit9";
0386     case I915_BIT_6_SWIZZLE_9_10:
0387         return "bit9/bit10";
0388     case I915_BIT_6_SWIZZLE_9_11:
0389         return "bit9/bit11";
0390     case I915_BIT_6_SWIZZLE_9_10_11:
0391         return "bit9/bit10/bit11";
0392     case I915_BIT_6_SWIZZLE_9_17:
0393         return "bit9/bit17";
0394     case I915_BIT_6_SWIZZLE_9_10_17:
0395         return "bit9/bit10/bit17";
0396     case I915_BIT_6_SWIZZLE_UNKNOWN:
0397         return "unknown";
0398     }
0399 
0400     return "bug";
0401 }
0402 
0403 static int i915_swizzle_info(struct seq_file *m, void *data)
0404 {
0405     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0406     struct intel_uncore *uncore = &dev_priv->uncore;
0407     intel_wakeref_t wakeref;
0408 
0409     seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
0410            swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
0411     seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
0412            swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
0413 
0414     if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
0415         seq_puts(m, "L-shaped memory detected\n");
0416 
0417     /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
0418     if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
0419         return 0;
0420 
0421     wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
0422 
0423     if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {
0424         seq_printf(m, "DDC = 0x%08x\n",
0425                intel_uncore_read(uncore, DCC));
0426         seq_printf(m, "DDC2 = 0x%08x\n",
0427                intel_uncore_read(uncore, DCC2));
0428         seq_printf(m, "C0DRB3 = 0x%04x\n",
0429                intel_uncore_read16(uncore, C0DRB3_BW));
0430         seq_printf(m, "C1DRB3 = 0x%04x\n",
0431                intel_uncore_read16(uncore, C1DRB3_BW));
0432     } else if (GRAPHICS_VER(dev_priv) >= 6) {
0433         seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
0434                intel_uncore_read(uncore, MAD_DIMM_C0));
0435         seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
0436                intel_uncore_read(uncore, MAD_DIMM_C1));
0437         seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
0438                intel_uncore_read(uncore, MAD_DIMM_C2));
0439         seq_printf(m, "TILECTL = 0x%08x\n",
0440                intel_uncore_read(uncore, TILECTL));
0441         if (GRAPHICS_VER(dev_priv) >= 8)
0442             seq_printf(m, "GAMTARBMODE = 0x%08x\n",
0443                    intel_uncore_read(uncore, GAMTARBMODE));
0444         else
0445             seq_printf(m, "ARB_MODE = 0x%08x\n",
0446                    intel_uncore_read(uncore, ARB_MODE));
0447         seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
0448                intel_uncore_read(uncore, DISP_ARB_CTL));
0449     }
0450 
0451     intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
0452 
0453     return 0;
0454 }
0455 
0456 static int i915_rps_boost_info(struct seq_file *m, void *data)
0457 {
0458     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0459     struct intel_rps *rps = &to_gt(dev_priv)->rps;
0460 
0461     seq_printf(m, "RPS enabled? %s\n",
0462            str_yes_no(intel_rps_is_enabled(rps)));
0463     seq_printf(m, "RPS active? %s\n",
0464            str_yes_no(intel_rps_is_active(rps)));
0465     seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake));
0466     seq_printf(m, "Boosts outstanding? %d\n",
0467            atomic_read(&rps->num_waiters));
0468     seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
0469     seq_printf(m, "Frequency requested %d, actual %d\n",
0470            intel_gpu_freq(rps, rps->cur_freq),
0471            intel_rps_read_actual_frequency(rps));
0472     seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
0473            intel_gpu_freq(rps, rps->min_freq),
0474            intel_gpu_freq(rps, rps->min_freq_softlimit),
0475            intel_gpu_freq(rps, rps->max_freq_softlimit),
0476            intel_gpu_freq(rps, rps->max_freq));
0477     seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
0478            intel_gpu_freq(rps, rps->idle_freq),
0479            intel_gpu_freq(rps, rps->efficient_freq),
0480            intel_gpu_freq(rps, rps->boost_freq));
0481 
0482     seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
0483 
0484     return 0;
0485 }
0486 
0487 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
0488 {
0489     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0490     struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
0491 
0492     if (!HAS_RUNTIME_PM(dev_priv))
0493         seq_puts(m, "Runtime power management not supported\n");
0494 
0495     seq_printf(m, "Runtime power status: %s\n",
0496            str_enabled_disabled(!dev_priv->power_domains.init_wakeref));
0497 
0498     seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake));
0499     seq_printf(m, "IRQs disabled: %s\n",
0500            str_yes_no(!intel_irqs_enabled(dev_priv)));
0501 #ifdef CONFIG_PM
0502     seq_printf(m, "Usage count: %d\n",
0503            atomic_read(&dev_priv->drm.dev->power.usage_count));
0504 #else
0505     seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
0506 #endif
0507     seq_printf(m, "PCI device power state: %s [%d]\n",
0508            pci_power_name(pdev->current_state),
0509            pdev->current_state);
0510 
0511     if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
0512         struct drm_printer p = drm_seq_file_printer(m);
0513 
0514         print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
0515     }
0516 
0517     return 0;
0518 }
0519 
0520 static int i915_engine_info(struct seq_file *m, void *unused)
0521 {
0522     struct drm_i915_private *i915 = node_to_i915(m->private);
0523     struct intel_engine_cs *engine;
0524     intel_wakeref_t wakeref;
0525     struct drm_printer p;
0526 
0527     wakeref = intel_runtime_pm_get(&i915->runtime_pm);
0528 
0529     seq_printf(m, "GT awake? %s [%d], %llums\n",
0530            str_yes_no(to_gt(i915)->awake),
0531            atomic_read(&to_gt(i915)->wakeref.count),
0532            ktime_to_ms(intel_gt_get_awake_time(to_gt(i915))));
0533     seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
0534            to_gt(i915)->clock_frequency,
0535            to_gt(i915)->clock_period_ns);
0536 
0537     p = drm_seq_file_printer(m);
0538     for_each_uabi_engine(engine, i915)
0539         intel_engine_dump(engine, &p, "%s\n", engine->name);
0540 
0541     intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule);
0542 
0543     intel_runtime_pm_put(&i915->runtime_pm, wakeref);
0544 
0545     return 0;
0546 }
0547 
0548 static int i915_wa_registers(struct seq_file *m, void *unused)
0549 {
0550     struct drm_i915_private *i915 = node_to_i915(m->private);
0551     struct intel_engine_cs *engine;
0552 
0553     for_each_uabi_engine(engine, i915) {
0554         const struct i915_wa_list *wal = &engine->ctx_wa_list;
0555         const struct i915_wa *wa;
0556         unsigned int count;
0557 
0558         count = wal->count;
0559         if (!count)
0560             continue;
0561 
0562         seq_printf(m, "%s: Workarounds applied: %u\n",
0563                engine->name, count);
0564 
0565         for (wa = wal->list; count--; wa++)
0566             seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
0567                    i915_mmio_reg_offset(wa->reg),
0568                    wa->set, wa->clr);
0569 
0570         seq_printf(m, "\n");
0571     }
0572 
0573     return 0;
0574 }
0575 
0576 static int i915_wedged_get(void *data, u64 *val)
0577 {
0578     struct drm_i915_private *i915 = data;
0579 
0580     return intel_gt_debugfs_reset_show(to_gt(i915), val);
0581 }
0582 
0583 static int i915_wedged_set(void *data, u64 val)
0584 {
0585     struct drm_i915_private *i915 = data;
0586     intel_gt_debugfs_reset_store(to_gt(i915), val);
0587 
0588     return 0;
0589 }
0590 
0591 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
0592             i915_wedged_get, i915_wedged_set,
0593             "%llu\n");
0594 
0595 static int
0596 i915_perf_noa_delay_set(void *data, u64 val)
0597 {
0598     struct drm_i915_private *i915 = data;
0599 
0600     /*
0601      * This would lead to infinite waits as we're doing timestamp
0602      * difference on the CS with only 32bits.
0603      */
0604     if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX)
0605         return -EINVAL;
0606 
0607     atomic64_set(&i915->perf.noa_programming_delay, val);
0608     return 0;
0609 }
0610 
0611 static int
0612 i915_perf_noa_delay_get(void *data, u64 *val)
0613 {
0614     struct drm_i915_private *i915 = data;
0615 
0616     *val = atomic64_read(&i915->perf.noa_programming_delay);
0617     return 0;
0618 }
0619 
0620 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
0621             i915_perf_noa_delay_get,
0622             i915_perf_noa_delay_set,
0623             "%llu\n");
0624 
0625 #define DROP_UNBOUND    BIT(0)
0626 #define DROP_BOUND  BIT(1)
0627 #define DROP_RETIRE BIT(2)
0628 #define DROP_ACTIVE BIT(3)
0629 #define DROP_FREED  BIT(4)
0630 #define DROP_SHRINK_ALL BIT(5)
0631 #define DROP_IDLE   BIT(6)
0632 #define DROP_RESET_ACTIVE   BIT(7)
0633 #define DROP_RESET_SEQNO    BIT(8)
0634 #define DROP_RCU    BIT(9)
0635 #define DROP_ALL (DROP_UNBOUND  | \
0636           DROP_BOUND    | \
0637           DROP_RETIRE   | \
0638           DROP_ACTIVE   | \
0639           DROP_FREED    | \
0640           DROP_SHRINK_ALL |\
0641           DROP_IDLE | \
0642           DROP_RESET_ACTIVE | \
0643           DROP_RESET_SEQNO | \
0644           DROP_RCU)
0645 static int
0646 i915_drop_caches_get(void *data, u64 *val)
0647 {
0648     *val = DROP_ALL;
0649 
0650     return 0;
0651 }
0652 static int
0653 gt_drop_caches(struct intel_gt *gt, u64 val)
0654 {
0655     int ret;
0656 
0657     if (val & DROP_RESET_ACTIVE &&
0658         wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT))
0659         intel_gt_set_wedged(gt);
0660 
0661     if (val & DROP_RETIRE)
0662         intel_gt_retire_requests(gt);
0663 
0664     if (val & (DROP_IDLE | DROP_ACTIVE)) {
0665         ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
0666         if (ret)
0667             return ret;
0668     }
0669 
0670     if (val & DROP_IDLE) {
0671         ret = intel_gt_pm_wait_for_idle(gt);
0672         if (ret)
0673             return ret;
0674     }
0675 
0676     if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
0677         intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
0678 
0679     if (val & DROP_FREED)
0680         intel_gt_flush_buffer_pool(gt);
0681 
0682     return 0;
0683 }
0684 
0685 static int
0686 i915_drop_caches_set(void *data, u64 val)
0687 {
0688     struct drm_i915_private *i915 = data;
0689     unsigned int flags;
0690     int ret;
0691 
0692     DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
0693           val, val & DROP_ALL);
0694 
0695     ret = gt_drop_caches(to_gt(i915), val);
0696     if (ret)
0697         return ret;
0698 
0699     fs_reclaim_acquire(GFP_KERNEL);
0700     flags = memalloc_noreclaim_save();
0701     if (val & DROP_BOUND)
0702         i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
0703 
0704     if (val & DROP_UNBOUND)
0705         i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
0706 
0707     if (val & DROP_SHRINK_ALL)
0708         i915_gem_shrink_all(i915);
0709     memalloc_noreclaim_restore(flags);
0710     fs_reclaim_release(GFP_KERNEL);
0711 
0712     if (val & DROP_RCU)
0713         rcu_barrier();
0714 
0715     if (val & DROP_FREED)
0716         i915_gem_drain_freed_objects(i915);
0717 
0718     return 0;
0719 }
0720 
0721 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
0722             i915_drop_caches_get, i915_drop_caches_set,
0723             "0x%08llx\n");
0724 
0725 static int i915_sseu_status(struct seq_file *m, void *unused)
0726 {
0727     struct drm_i915_private *i915 = node_to_i915(m->private);
0728     struct intel_gt *gt = to_gt(i915);
0729 
0730     return intel_sseu_status(m, gt);
0731 }
0732 
0733 static int i915_forcewake_open(struct inode *inode, struct file *file)
0734 {
0735     struct drm_i915_private *i915 = inode->i_private;
0736     intel_gt_pm_debugfs_forcewake_user_open(to_gt(i915));
0737 
0738     return 0;
0739 }
0740 
0741 static int i915_forcewake_release(struct inode *inode, struct file *file)
0742 {
0743     struct drm_i915_private *i915 = inode->i_private;
0744     intel_gt_pm_debugfs_forcewake_user_release(to_gt(i915));
0745 
0746     return 0;
0747 }
0748 
0749 static const struct file_operations i915_forcewake_fops = {
0750     .owner = THIS_MODULE,
0751     .open = i915_forcewake_open,
0752     .release = i915_forcewake_release,
0753 };
0754 
0755 static const struct drm_info_list i915_debugfs_list[] = {
0756     {"i915_capabilities", i915_capabilities, 0},
0757     {"i915_gem_objects", i915_gem_object_info, 0},
0758     {"i915_frequency_info", i915_frequency_info, 0},
0759     {"i915_swizzle_info", i915_swizzle_info, 0},
0760     {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
0761     {"i915_engine_info", i915_engine_info, 0},
0762     {"i915_wa_registers", i915_wa_registers, 0},
0763     {"i915_sseu_status", i915_sseu_status, 0},
0764     {"i915_rps_boost_info", i915_rps_boost_info, 0},
0765 };
0766 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
0767 
0768 static const struct i915_debugfs_files {
0769     const char *name;
0770     const struct file_operations *fops;
0771 } i915_debugfs_files[] = {
0772     {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
0773     {"i915_wedged", &i915_wedged_fops},
0774     {"i915_gem_drop_caches", &i915_drop_caches_fops},
0775 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
0776     {"i915_error_state", &i915_error_state_fops},
0777     {"i915_gpu_info", &i915_gpu_info_fops},
0778 #endif
0779 };
0780 
0781 void i915_debugfs_register(struct drm_i915_private *dev_priv)
0782 {
0783     struct drm_minor *minor = dev_priv->drm.primary;
0784     int i;
0785 
0786     i915_debugfs_params(dev_priv);
0787 
0788     debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
0789                 to_i915(minor->dev), &i915_forcewake_fops);
0790     for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
0791         debugfs_create_file(i915_debugfs_files[i].name,
0792                     S_IRUGO | S_IWUSR,
0793                     minor->debugfs_root,
0794                     to_i915(minor->dev),
0795                     i915_debugfs_files[i].fops);
0796     }
0797 
0798     drm_debugfs_create_files(i915_debugfs_list,
0799                  I915_DEBUGFS_ENTRIES,
0800                  minor->debugfs_root, minor);
0801 }
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