gt/uc/intel_guc.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2014-2019 Intel Corporation
0004  */
0005
0006 #ifndef _INTEL_GUC_H_
0007 #define _INTEL_GUC_H_
0008
0009 #include <linux/delay.h>
0010 #include <linux/iosys-map.h>
0011 #include <linux/xarray.h>
0012
0013 #include "intel_guc_ct.h"
0014 #include "intel_guc_fw.h"
0015 #include "intel_guc_fwif.h"
0016 #include "intel_guc_log.h"
0017 #include "intel_guc_reg.h"
0018 #include "intel_guc_slpc_types.h"
0019 #include "intel_uc_fw.h"
0020 #include "intel_uncore.h"
0021 #include "i915_utils.h"
0022 #include "i915_vma.h"
0023
0024 struct __guc_ads_blob;
0025 struct intel_guc_state_capture;
0026
0027 /**
0028  * struct intel_guc - Top level structure of GuC.
0029  *
0030  * It handles firmware loading and manages client pool. intel_guc owns an
0031  * i915_sched_engine for submission.
0032  */
0033 struct intel_guc {
0034     /** @fw: the GuC firmware */
0035     struct intel_uc_fw fw;
0036     /** @log: sub-structure containing GuC log related data and objects */
0037     struct intel_guc_log log;
0038     /** @ct: the command transport communication channel */
0039     struct intel_guc_ct ct;
0040     /** @slpc: sub-structure containing SLPC related data and objects */
0041     struct intel_guc_slpc slpc;
0042     /** @capture: the error-state-capture module's data and objects */
0043     struct intel_guc_state_capture *capture;
0044
0045     /** @sched_engine: Global engine used to submit requests to GuC */
0046     struct i915_sched_engine *sched_engine;
0047     /**
0048      * @stalled_request: if GuC can't process a request for any reason, we
0049      * save it until GuC restarts processing. No other request can be
0050      * submitted until the stalled request is processed.
0051      */
0052     struct i915_request *stalled_request;
0053     /**
0054      * @submission_stall_reason: reason why submission is stalled
0055      */
0056     enum {
0057         STALL_NONE,
0058         STALL_REGISTER_CONTEXT,
0059         STALL_MOVE_LRC_TAIL,
0060         STALL_ADD_REQUEST,
0061     } submission_stall_reason;
0062
0063     /* intel_guc_recv interrupt related state */
0064     /** @irq_lock: protects GuC irq state */
0065     spinlock_t irq_lock;
0066     /**
0067      * @msg_enabled_mask: mask of events that are processed when receiving
0068      * an INTEL_GUC_ACTION_DEFAULT G2H message.
0069      */
0070     unsigned int msg_enabled_mask;
0071
0072     /**
0073      * @outstanding_submission_g2h: number of outstanding GuC to Host
0074      * responses related to GuC submission, used to determine if the GT is
0075      * idle
0076      */
0077     atomic_t outstanding_submission_g2h;
0078
0079     /** @interrupts: pointers to GuC interrupt-managing functions. */
0080     struct {
0081         void (*reset)(struct intel_guc *guc);
0082         void (*enable)(struct intel_guc *guc);
0083         void (*disable)(struct intel_guc *guc);
0084     } interrupts;
0085
0086     /**
0087      * @submission_state: sub-structure for submission state protected by
0088      * single lock
0089      */
0090     struct {
0091         /**
0092          * @lock: protects everything in submission_state,
0093          * ce->guc_id.id, and ce->guc_id.ref when transitioning in and
0094          * out of zero
0095          */
0096         spinlock_t lock;
0097         /**
0098          * @guc_ids: used to allocate new guc_ids, single-lrc
0099          */
0100         struct ida guc_ids;
0101         /**
0102          * @num_guc_ids: Number of guc_ids, selftest feature to be able
0103          * to reduce this number while testing.
0104          */
0105         int num_guc_ids;
0106         /**
0107          * @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc
0108          */
0109         unsigned long *guc_ids_bitmap;
0110         /**
0111          * @guc_id_list: list of intel_context with valid guc_ids but no
0112          * refs
0113          */
0114         struct list_head guc_id_list;
0115         /**
0116          * @destroyed_contexts: list of contexts waiting to be destroyed
0117          * (deregistered with the GuC)
0118          */
0119         struct list_head destroyed_contexts;
0120         /**
0121          * @destroyed_worker: worker to deregister contexts, need as we
0122          * need to take a GT PM reference and can't from destroy
0123          * function as it might be in an atomic context (no sleeping)
0124          */
0125         struct work_struct destroyed_worker;
0126         /**
0127          * @reset_fail_worker: worker to trigger a GT reset after an
0128          * engine reset fails
0129          */
0130         struct work_struct reset_fail_worker;
0131         /**
0132          * @reset_fail_mask: mask of engines that failed to reset
0133          */
0134         intel_engine_mask_t reset_fail_mask;
0135     } submission_state;
0136
0137     /**
0138      * @submission_supported: tracks whether we support GuC submission on
0139      * the current platform
0140      */
0141     bool submission_supported;
0142     /** @submission_selected: tracks whether the user enabled GuC submission */
0143     bool submission_selected;
0144     /** @submission_initialized: tracks whether GuC submission has been initialised */
0145     bool submission_initialized;
0146     /**
0147      * @rc_supported: tracks whether we support GuC rc on the current platform
0148      */
0149     bool rc_supported;
0150     /** @rc_selected: tracks whether the user enabled GuC rc */
0151     bool rc_selected;
0152
0153     /** @ads_vma: object allocated to hold the GuC ADS */
0154     struct i915_vma *ads_vma;
0155     /** @ads_map: contents of the GuC ADS */
0156     struct iosys_map ads_map;
0157     /** @ads_regset_size: size of the save/restore regsets in the ADS */
0158     u32 ads_regset_size;
0159     /**
0160      * @ads_regset_count: number of save/restore registers in the ADS for
0161      * each engine
0162      */
0163     u32 ads_regset_count[I915_NUM_ENGINES];
0164     /** @ads_regset: save/restore regsets in the ADS */
0165     struct guc_mmio_reg *ads_regset;
0166     /** @ads_golden_ctxt_size: size of the golden contexts in the ADS */
0167     u32 ads_golden_ctxt_size;
0168     /** @ads_capture_size: size of register lists in the ADS used for error capture */
0169     u32 ads_capture_size;
0170     /** @ads_engine_usage_size: size of engine usage in the ADS */
0171     u32 ads_engine_usage_size;
0172
0173     /** @lrc_desc_pool_v69: object allocated to hold the GuC LRC descriptor pool */
0174     struct i915_vma *lrc_desc_pool_v69;
0175     /** @lrc_desc_pool_vaddr_v69: contents of the GuC LRC descriptor pool */
0176     void *lrc_desc_pool_vaddr_v69;
0177
0178     /**
0179      * @context_lookup: used to resolve intel_context from guc_id, if a
0180      * context is present in this structure it is registered with the GuC
0181      */
0182     struct xarray context_lookup;
0183
0184     /** @params: Control params for fw initialization */
0185     u32 params[GUC_CTL_MAX_DWORDS];
0186
0187     /** @send_regs: GuC's FW specific registers used for sending MMIO H2G */
0188     struct {
0189         u32 base;
0190         unsigned int count;
0191         enum forcewake_domains fw_domains;
0192     } send_regs;
0193
0194     /** @notify_reg: register used to send interrupts to the GuC FW */
0195     i915_reg_t notify_reg;
0196
0197     /**
0198      * @mmio_msg: notification bitmask that the GuC writes in one of its
0199      * registers when the CT channel is disabled, to be processed when the
0200      * channel is back up.
0201      */
0202     u32 mmio_msg;
0203
0204     /** @send_mutex: used to serialize the intel_guc_send actions */
0205     struct mutex send_mutex;
0206
0207     /**
0208      * @timestamp: GT timestamp object that stores a copy of the timestamp
0209      * and adjusts it for overflow using a worker.
0210      */
0211     struct {
0212         /**
0213          * @lock: Lock protecting the below fields and the engine stats.
0214          */
0215         spinlock_t lock;
0216
0217         /**
0218          * @gt_stamp: 64 bit extended value of the GT timestamp.
0219          */
0220         u64 gt_stamp;
0221
0222         /**
0223          * @ping_delay: Period for polling the GT timestamp for
0224          * overflow.
0225          */
0226         unsigned long ping_delay;
0227
0228         /**
0229          * @work: Periodic work to adjust GT timestamp, engine and
0230          * context usage for overflows.
0231          */
0232         struct delayed_work work;
0233
0234         /**
0235          * @shift: Right shift value for the gpm timestamp
0236          */
0237         u32 shift;
0238
0239         /**
0240          * @last_stat_jiffies: jiffies at last actual stats collection time
0241          * We use this timestamp to ensure we don't oversample the
0242          * stats because runtime power management events can trigger
0243          * stats collection at much higher rates than required.
0244          */
0245         unsigned long last_stat_jiffies;
0246     } timestamp;
0247
0248 #ifdef CONFIG_DRM_I915_SELFTEST
0249     /**
0250      * @number_guc_id_stolen: The number of guc_ids that have been stolen
0251      */
0252     int number_guc_id_stolen;
0253 #endif
0254 };
0255
0256 static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
0257 {
0258     return container_of(log, struct intel_guc, log);
0259 }
0260
0261 static
0262 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
0263 {
0264     return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, 0);
0265 }
0266
0267 static
0268 inline int intel_guc_send_nb(struct intel_guc *guc, const u32 *action, u32 len,
0269                  u32 g2h_len_dw)
0270 {
0271     return intel_guc_ct_send(&guc->ct, action, len, NULL, 0,
0272                  MAKE_SEND_FLAGS(g2h_len_dw));
0273 }
0274
0275 static inline int
0276 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
0277                u32 *response_buf, u32 response_buf_size)
0278 {
0279     return intel_guc_ct_send(&guc->ct, action, len,
0280                  response_buf, response_buf_size, 0);
0281 }
0282
0283 static inline int intel_guc_send_busy_loop(struct intel_guc *guc,
0284                        const u32 *action,
0285                        u32 len,
0286                        u32 g2h_len_dw,
0287                        bool loop)
0288 {
0289     int err;
0290     unsigned int sleep_period_ms = 1;
0291     bool not_atomic = !in_atomic() && !irqs_disabled();
0292
0293     /*
0294      * FIXME: Have caller pass in if we are in an atomic context to avoid
0295      * using in_atomic(). It is likely safe here as we check for irqs
0296      * disabled which basically all the spin locks in the i915 do but
0297      * regardless this should be cleaned up.
0298      */
0299
0300     /* No sleeping with spin locks, just busy loop */
0301     might_sleep_if(loop && not_atomic);
0302
0303 retry:
0304     err = intel_guc_send_nb(guc, action, len, g2h_len_dw);
0305     if (unlikely(err == -EBUSY && loop)) {
0306         if (likely(not_atomic)) {
0307             if (msleep_interruptible(sleep_period_ms))
0308                 return -EINTR;
0309             sleep_period_ms = sleep_period_ms << 1;
0310         } else {
0311             cpu_relax();
0312         }
0313         goto retry;
0314     }
0315
0316     return err;
0317 }
0318
0319 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
0320 {
0321     intel_guc_ct_event_handler(&guc->ct);
0322 }
0323
0324 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
0325 #define GUC_GGTT_TOP    0xFEE00000
0326
0327 /**
0328  * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
0329  * @guc: intel_guc structure.
0330  * @vma: i915 graphics virtual memory area.
0331  *
0332  * GuC does not allow any gfx GGTT address that falls into range
0333  * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
0334  * Currently, in order to exclude [0, ggtt.pin_bias) address space from
0335  * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
0336  * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
0337  *
0338  * Return: GGTT offset of the @vma.
0339  */
0340 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
0341                     struct i915_vma *vma)
0342 {
0343     u32 offset = i915_ggtt_offset(vma);
0344
0345     GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
0346     GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
0347
0348     return offset;
0349 }
0350
0351 void intel_guc_init_early(struct intel_guc *guc);
0352 void intel_guc_init_late(struct intel_guc *guc);
0353 void intel_guc_init_send_regs(struct intel_guc *guc);
0354 void intel_guc_write_params(struct intel_guc *guc);
0355 int intel_guc_init(struct intel_guc *guc);
0356 void intel_guc_fini(struct intel_guc *guc);
0357 void intel_guc_notify(struct intel_guc *guc);
0358 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
0359             u32 *response_buf, u32 response_buf_size);
0360 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
0361                        const u32 *payload, u32 len);
0362 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
0363 int intel_guc_suspend(struct intel_guc *guc);
0364 int intel_guc_resume(struct intel_guc *guc);
0365 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
0366 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,
0367                    struct i915_vma **out_vma, void **out_vaddr);
0368 int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value);
0369 int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value);
0370
0371 static inline bool intel_guc_is_supported(struct intel_guc *guc)
0372 {
0373     return intel_uc_fw_is_supported(&guc->fw);
0374 }
0375
0376 static inline bool intel_guc_is_wanted(struct intel_guc *guc)
0377 {
0378     return intel_uc_fw_is_enabled(&guc->fw);
0379 }
0380
0381 static inline bool intel_guc_is_used(struct intel_guc *guc)
0382 {
0383     GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED);
0384     return intel_uc_fw_is_available(&guc->fw);
0385 }
0386
0387 static inline bool intel_guc_is_fw_running(struct intel_guc *guc)
0388 {
0389     return intel_uc_fw_is_running(&guc->fw);
0390 }
0391
0392 static inline bool intel_guc_is_ready(struct intel_guc *guc)
0393 {
0394     return intel_guc_is_fw_running(guc) && intel_guc_ct_enabled(&guc->ct);
0395 }
0396
0397 static inline void intel_guc_reset_interrupts(struct intel_guc *guc)
0398 {
0399     guc->interrupts.reset(guc);
0400 }
0401
0402 static inline void intel_guc_enable_interrupts(struct intel_guc *guc)
0403 {
0404     guc->interrupts.enable(guc);
0405 }
0406
0407 static inline void intel_guc_disable_interrupts(struct intel_guc *guc)
0408 {
0409     guc->interrupts.disable(guc);
0410 }
0411
0412 static inline int intel_guc_sanitize(struct intel_guc *guc)
0413 {
0414     intel_uc_fw_sanitize(&guc->fw);
0415     intel_guc_disable_interrupts(guc);
0416     intel_guc_ct_sanitize(&guc->ct);
0417     guc->mmio_msg = 0;
0418
0419     return 0;
0420 }
0421
0422 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
0423 {
0424     spin_lock_irq(&guc->irq_lock);
0425     guc->msg_enabled_mask |= mask;
0426     spin_unlock_irq(&guc->irq_lock);
0427 }
0428
0429 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
0430 {
0431     spin_lock_irq(&guc->irq_lock);
0432     guc->msg_enabled_mask &= ~mask;
0433     spin_unlock_irq(&guc->irq_lock);
0434 }
0435
0436 int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout);
0437
0438 int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
0439                       const u32 *msg, u32 len);
0440 int intel_guc_sched_done_process_msg(struct intel_guc *guc,
0441                      const u32 *msg, u32 len);
0442 int intel_guc_context_reset_process_msg(struct intel_guc *guc,
0443                     const u32 *msg, u32 len);
0444 int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
0445                      const u32 *msg, u32 len);
0446 int intel_guc_error_capture_process_msg(struct intel_guc *guc,
0447                     const u32 *msg, u32 len);
0448
0449 struct intel_engine_cs *
0450 intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance);
0451
0452 void intel_guc_find_hung_context(struct intel_engine_cs *engine);
0453
0454 int intel_guc_global_policies_update(struct intel_guc *guc);
0455
0456 void intel_guc_context_ban(struct intel_context *ce, struct i915_request *rq);
0457
0458 void intel_guc_submission_reset_prepare(struct intel_guc *guc);
0459 void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled);
0460 void intel_guc_submission_reset_finish(struct intel_guc *guc);
0461 void intel_guc_submission_cancel_requests(struct intel_guc *guc);
0462
0463 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
0464
0465 void intel_guc_write_barrier(struct intel_guc *guc);
0466
0467 #endif