0001
0002
0003
0004
0005
0006 #define NUM_STEPS 5
0007 #define H2G_DELAY 50000
0008 #define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 10000)
0009 #define FREQUENCY_REQ_UNIT DIV_ROUND_CLOSEST(GT_FREQUENCY_MULTIPLIER, \
0010 GEN9_FREQ_SCALER)
0011 enum test_type {
0012 VARY_MIN,
0013 VARY_MAX,
0014 MAX_GRANTED
0015 };
0016
0017 static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq)
0018 {
0019 int ret;
0020
0021 ret = intel_guc_slpc_set_min_freq(slpc, freq);
0022 if (ret)
0023 pr_err("Could not set min frequency to [%u]\n", freq);
0024 else
0025 delay_for_h2g();
0026
0027 return ret;
0028 }
0029
0030 static int slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 freq)
0031 {
0032 int ret;
0033
0034 ret = intel_guc_slpc_set_max_freq(slpc, freq);
0035 if (ret)
0036 pr_err("Could not set maximum frequency [%u]\n",
0037 freq);
0038 else
0039 delay_for_h2g();
0040
0041 return ret;
0042 }
0043
0044 static int vary_max_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps,
0045 u32 *max_act_freq)
0046 {
0047 u32 step, max_freq, req_freq;
0048 u32 act_freq;
0049 int err = 0;
0050
0051
0052 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS;
0053 *max_act_freq = slpc->min_freq;
0054 for (max_freq = slpc->rp0_freq; max_freq > slpc->min_freq;
0055 max_freq -= step) {
0056 err = slpc_set_max_freq(slpc, max_freq);
0057 if (err)
0058 break;
0059
0060 req_freq = intel_rps_read_punit_req_frequency(rps);
0061
0062
0063 if (req_freq > (max_freq + FREQUENCY_REQ_UNIT)) {
0064 pr_err("SWReq is %d, should be at most %d\n", req_freq,
0065 max_freq + FREQUENCY_REQ_UNIT);
0066 err = -EINVAL;
0067 }
0068
0069 act_freq = intel_rps_read_actual_frequency(rps);
0070 if (act_freq > *max_act_freq)
0071 *max_act_freq = act_freq;
0072
0073 if (err)
0074 break;
0075 }
0076
0077 return err;
0078 }
0079
0080 static int vary_min_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps,
0081 u32 *max_act_freq)
0082 {
0083 u32 step, min_freq, req_freq;
0084 u32 act_freq;
0085 int err = 0;
0086
0087
0088 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS;
0089 *max_act_freq = slpc->min_freq;
0090 for (min_freq = slpc->min_freq; min_freq < slpc->rp0_freq;
0091 min_freq += step) {
0092 err = slpc_set_min_freq(slpc, min_freq);
0093 if (err)
0094 break;
0095
0096 req_freq = intel_rps_read_punit_req_frequency(rps);
0097
0098
0099 if (req_freq < (min_freq - FREQUENCY_REQ_UNIT)) {
0100 pr_err("SWReq is %d, should be at least %d\n", req_freq,
0101 min_freq - FREQUENCY_REQ_UNIT);
0102 err = -EINVAL;
0103 }
0104
0105 act_freq = intel_rps_read_actual_frequency(rps);
0106 if (act_freq > *max_act_freq)
0107 *max_act_freq = act_freq;
0108
0109 if (err)
0110 break;
0111 }
0112
0113 return err;
0114 }
0115
0116 static int max_granted_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, u32 *max_act_freq)
0117 {
0118 struct intel_gt *gt = rps_to_gt(rps);
0119 u32 perf_limit_reasons;
0120 int err = 0;
0121
0122 err = slpc_set_min_freq(slpc, slpc->rp0_freq);
0123 if (err)
0124 return err;
0125
0126 *max_act_freq = intel_rps_read_actual_frequency(rps);
0127 if (*max_act_freq != slpc->rp0_freq) {
0128
0129 perf_limit_reasons = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
0130
0131
0132 if (!(perf_limit_reasons & GT0_PERF_LIMIT_REASONS_MASK)) {
0133 pr_err("Pcode did not grant max freq\n");
0134 err = -EINVAL;
0135 } else {
0136 pr_info("Pcode throttled frequency 0x%x\n", perf_limit_reasons);
0137 }
0138 }
0139
0140 return err;
0141 }
0142
0143 static int run_test(struct intel_gt *gt, int test_type)
0144 {
0145 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
0146 struct intel_rps *rps = >->rps;
0147 struct intel_engine_cs *engine;
0148 enum intel_engine_id id;
0149 struct igt_spinner spin;
0150 u32 slpc_min_freq, slpc_max_freq;
0151 int err = 0;
0152
0153 if (!intel_uc_uses_guc_slpc(>->uc))
0154 return 0;
0155
0156 if (igt_spinner_init(&spin, gt))
0157 return -ENOMEM;
0158
0159 if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
0160 pr_err("Could not get SLPC max freq\n");
0161 return -EIO;
0162 }
0163
0164 if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
0165 pr_err("Could not get SLPC min freq\n");
0166 return -EIO;
0167 }
0168
0169 if (slpc->min_freq == slpc->rp0_freq) {
0170 pr_err("Min/Max are fused to the same value\n");
0171 return -EINVAL;
0172 }
0173
0174 intel_gt_pm_wait_for_idle(gt);
0175 intel_gt_pm_get(gt);
0176 for_each_engine(engine, gt, id) {
0177 struct i915_request *rq;
0178 u32 max_act_freq;
0179
0180 if (!intel_engine_can_store_dword(engine))
0181 continue;
0182
0183 st_engine_heartbeat_disable(engine);
0184
0185 rq = igt_spinner_create_request(&spin,
0186 engine->kernel_context,
0187 MI_NOOP);
0188 if (IS_ERR(rq)) {
0189 err = PTR_ERR(rq);
0190 st_engine_heartbeat_enable(engine);
0191 break;
0192 }
0193
0194 i915_request_add(rq);
0195
0196 if (!igt_wait_for_spinner(&spin, rq)) {
0197 pr_err("%s: Spinner did not start\n",
0198 engine->name);
0199 igt_spinner_end(&spin);
0200 st_engine_heartbeat_enable(engine);
0201 intel_gt_set_wedged(engine->gt);
0202 err = -EIO;
0203 break;
0204 }
0205
0206 switch (test_type) {
0207 case VARY_MIN:
0208 err = vary_min_freq(slpc, rps, &max_act_freq);
0209 break;
0210
0211 case VARY_MAX:
0212 err = vary_max_freq(slpc, rps, &max_act_freq);
0213 break;
0214
0215 case MAX_GRANTED:
0216
0217 if (engine->class == VIDEO_DECODE_CLASS ||
0218 engine->class == VIDEO_ENHANCEMENT_CLASS) {
0219 igt_spinner_end(&spin);
0220 st_engine_heartbeat_enable(engine);
0221 err = 0;
0222 continue;
0223 }
0224
0225 err = max_granted_freq(slpc, rps, &max_act_freq);
0226 break;
0227 }
0228
0229 pr_info("Max actual frequency for %s was %d\n",
0230 engine->name, max_act_freq);
0231
0232
0233 if (max_act_freq <= slpc_min_freq) {
0234 pr_err("Actual freq did not rise above min\n");
0235 pr_err("Perf Limit Reasons: 0x%x\n",
0236 intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS));
0237 err = -EINVAL;
0238 }
0239
0240 igt_spinner_end(&spin);
0241 st_engine_heartbeat_enable(engine);
0242
0243 if (err)
0244 break;
0245 }
0246
0247
0248 slpc_set_max_freq(slpc, slpc_max_freq);
0249 slpc_set_min_freq(slpc, slpc_min_freq);
0250
0251 if (igt_flush_test(gt->i915))
0252 err = -EIO;
0253
0254 intel_gt_pm_put(gt);
0255 igt_spinner_fini(&spin);
0256 intel_gt_pm_wait_for_idle(gt);
0257
0258 return err;
0259 }
0260
0261 static int live_slpc_vary_min(void *arg)
0262 {
0263 struct drm_i915_private *i915 = arg;
0264 struct intel_gt *gt = to_gt(i915);
0265
0266 return run_test(gt, VARY_MIN);
0267 }
0268
0269 static int live_slpc_vary_max(void *arg)
0270 {
0271 struct drm_i915_private *i915 = arg;
0272 struct intel_gt *gt = to_gt(i915);
0273
0274 return run_test(gt, VARY_MAX);
0275 }
0276
0277
0278 static int live_slpc_max_granted(void *arg)
0279 {
0280 struct drm_i915_private *i915 = arg;
0281 struct intel_gt *gt = to_gt(i915);
0282
0283 return run_test(gt, MAX_GRANTED);
0284 }
0285
0286 int intel_slpc_live_selftests(struct drm_i915_private *i915)
0287 {
0288 static const struct i915_subtest tests[] = {
0289 SUBTEST(live_slpc_vary_max),
0290 SUBTEST(live_slpc_vary_min),
0291 SUBTEST(live_slpc_max_granted),
0292 };
0293
0294 if (intel_gt_is_wedged(to_gt(i915)))
0295 return 0;
0296
0297 return i915_live_subtests(tests, i915);
0298 }