i915/gt/selftest_mocs.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #include "gt/intel_engine_pm.h"
0007 #include "gt/intel_gpu_commands.h"
0008 #include "i915_selftest.h"
0009
0010 #include "gem/selftests/mock_context.h"
0011 #include "selftests/igt_reset.h"
0012 #include "selftests/igt_spinner.h"
0013 #include "selftests/intel_scheduler_helpers.h"
0014
0015 struct live_mocs {
0016     struct drm_i915_mocs_table table;
0017     struct drm_i915_mocs_table *mocs;
0018     struct drm_i915_mocs_table *l3cc;
0019     struct i915_vma *scratch;
0020     void *vaddr;
0021 };
0022
0023 static struct intel_context *mocs_context_create(struct intel_engine_cs *engine)
0024 {
0025     struct intel_context *ce;
0026
0027     ce = intel_context_create(engine);
0028     if (IS_ERR(ce))
0029         return ce;
0030
0031     /* We build large requests to read the registers from the ring */
0032     ce->ring_size = SZ_16K;
0033
0034     return ce;
0035 }
0036
0037 static int request_add_sync(struct i915_request *rq, int err)
0038 {
0039     i915_request_get(rq);
0040     i915_request_add(rq);
0041     if (i915_request_wait(rq, 0, HZ / 5) < 0)
0042         err = -ETIME;
0043     i915_request_put(rq);
0044
0045     return err;
0046 }
0047
0048 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
0049 {
0050     int err = 0;
0051
0052     i915_request_get(rq);
0053     i915_request_add(rq);
0054     if (spin && !igt_wait_for_spinner(spin, rq))
0055         err = -ETIME;
0056     i915_request_put(rq);
0057
0058     return err;
0059 }
0060
0061 static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
0062 {
0063     unsigned int flags;
0064     int err;
0065
0066     memset(arg, 0, sizeof(*arg));
0067
0068     flags = get_mocs_settings(gt->i915, &arg->table);
0069     if (!flags)
0070         return -EINVAL;
0071
0072     if (flags & HAS_RENDER_L3CC)
0073         arg->l3cc = &arg->table;
0074
0075     if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS))
0076         arg->mocs = &arg->table;
0077
0078     arg->scratch =
0079         __vm_create_scratch_for_read_pinned(&gt->ggtt->vm, PAGE_SIZE);
0080     if (IS_ERR(arg->scratch))
0081         return PTR_ERR(arg->scratch);
0082
0083     arg->vaddr = i915_gem_object_pin_map_unlocked(arg->scratch->obj, I915_MAP_WB);
0084     if (IS_ERR(arg->vaddr)) {
0085         err = PTR_ERR(arg->vaddr);
0086         goto err_scratch;
0087     }
0088
0089     return 0;
0090
0091 err_scratch:
0092     i915_vma_unpin_and_release(&arg->scratch, 0);
0093     return err;
0094 }
0095
0096 static void live_mocs_fini(struct live_mocs *arg)
0097 {
0098     i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
0099 }
0100
0101 static int read_regs(struct i915_request *rq,
0102              u32 addr, unsigned int count,
0103              u32 *offset)
0104 {
0105     unsigned int i;
0106     u32 *cs;
0107
0108     GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
0109
0110     cs = intel_ring_begin(rq, 4 * count);
0111     if (IS_ERR(cs))
0112         return PTR_ERR(cs);
0113
0114     for (i = 0; i < count; i++) {
0115         *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
0116         *cs++ = addr;
0117         *cs++ = *offset;
0118         *cs++ = 0;
0119
0120         addr += sizeof(u32);
0121         *offset += sizeof(u32);
0122     }
0123
0124     intel_ring_advance(rq, cs);
0125
0126     return 0;
0127 }
0128
0129 static int read_mocs_table(struct i915_request *rq,
0130                const struct drm_i915_mocs_table *table,
0131                u32 *offset)
0132 {
0133     u32 addr;
0134
0135     if (!table)
0136         return 0;
0137
0138     if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
0139         addr = global_mocs_offset();
0140     else
0141         addr = mocs_offset(rq->engine);
0142
0143     return read_regs(rq, addr, table->n_entries, offset);
0144 }
0145
0146 static int read_l3cc_table(struct i915_request *rq,
0147                const struct drm_i915_mocs_table *table,
0148                u32 *offset)
0149 {
0150     u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
0151
0152     if (!table)
0153         return 0;
0154
0155     return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
0156 }
0157
0158 static int check_mocs_table(struct intel_engine_cs *engine,
0159                 const struct drm_i915_mocs_table *table,
0160                 u32 **vaddr)
0161 {
0162     unsigned int i;
0163     u32 expect;
0164
0165     if (!table)
0166         return 0;
0167
0168     for_each_mocs(expect, table, i) {
0169         if (**vaddr != expect) {
0170             pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
0171                    engine->name, i, **vaddr, expect);
0172             return -EINVAL;
0173         }
0174         ++*vaddr;
0175     }
0176
0177     return 0;
0178 }
0179
0180 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
0181 {
0182     /*
0183      * Registers in this range are affected by the MCR selector
0184      * which only controls CPU initiated MMIO. Routing does not
0185      * work for CS access so we cannot verify them on this path.
0186      */
0187     return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
0188 }
0189
0190 static int check_l3cc_table(struct intel_engine_cs *engine,
0191                 const struct drm_i915_mocs_table *table,
0192                 u32 **vaddr)
0193 {
0194     /* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
0195     u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
0196     unsigned int i;
0197     u32 expect;
0198
0199     if (!table)
0200         return 0;
0201
0202     for_each_l3cc(expect, table, i) {
0203         if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
0204             pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
0205                    engine->name, i, **vaddr, expect);
0206             return -EINVAL;
0207         }
0208         ++*vaddr;
0209         reg += 4;
0210     }
0211
0212     return 0;
0213 }
0214
0215 static int check_mocs_engine(struct live_mocs *arg,
0216                  struct intel_context *ce)
0217 {
0218     struct i915_vma *vma = arg->scratch;
0219     struct i915_request *rq;
0220     u32 offset;
0221     u32 *vaddr;
0222     int err;
0223
0224     memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
0225
0226     rq = intel_context_create_request(ce);
0227     if (IS_ERR(rq))
0228         return PTR_ERR(rq);
0229
0230     i915_vma_lock(vma);
0231     err = i915_request_await_object(rq, vma->obj, true);
0232     if (!err)
0233         err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
0234     i915_vma_unlock(vma);
0235
0236     /* Read the mocs tables back using SRM */
0237     offset = i915_ggtt_offset(vma);
0238     if (!err)
0239         err = read_mocs_table(rq, arg->mocs, &offset);
0240     if (!err && ce->engine->class == RENDER_CLASS)
0241         err = read_l3cc_table(rq, arg->l3cc, &offset);
0242     offset -= i915_ggtt_offset(vma);
0243     GEM_BUG_ON(offset > PAGE_SIZE);
0244
0245     err = request_add_sync(rq, err);
0246     if (err)
0247         return err;
0248
0249     /* Compare the results against the expected tables */
0250     vaddr = arg->vaddr;
0251     if (!err)
0252         err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
0253     if (!err && ce->engine->class == RENDER_CLASS)
0254         err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
0255     if (err)
0256         return err;
0257
0258     GEM_BUG_ON(arg->vaddr + offset != vaddr);
0259     return 0;
0260 }
0261
0262 static int live_mocs_kernel(void *arg)
0263 {
0264     struct intel_gt *gt = arg;
0265     struct intel_engine_cs *engine;
0266     enum intel_engine_id id;
0267     struct live_mocs mocs;
0268     int err;
0269
0270     /* Basic check the system is configured with the expected mocs table */
0271
0272     err = live_mocs_init(&mocs, gt);
0273     if (err)
0274         return err;
0275
0276     for_each_engine(engine, gt, id) {
0277         intel_engine_pm_get(engine);
0278         err = check_mocs_engine(&mocs, engine->kernel_context);
0279         intel_engine_pm_put(engine);
0280         if (err)
0281             break;
0282     }
0283
0284     live_mocs_fini(&mocs);
0285     return err;
0286 }
0287
0288 static int live_mocs_clean(void *arg)
0289 {
0290     struct intel_gt *gt = arg;
0291     struct intel_engine_cs *engine;
0292     enum intel_engine_id id;
0293     struct live_mocs mocs;
0294     int err;
0295
0296     /* Every new context should see the same mocs table */
0297
0298     err = live_mocs_init(&mocs, gt);
0299     if (err)
0300         return err;
0301
0302     for_each_engine(engine, gt, id) {
0303         struct intel_context *ce;
0304
0305         ce = mocs_context_create(engine);
0306         if (IS_ERR(ce)) {
0307             err = PTR_ERR(ce);
0308             break;
0309         }
0310
0311         err = check_mocs_engine(&mocs, ce);
0312         intel_context_put(ce);
0313         if (err)
0314             break;
0315     }
0316
0317     live_mocs_fini(&mocs);
0318     return err;
0319 }
0320
0321 static int active_engine_reset(struct intel_context *ce,
0322                    const char *reason,
0323                    bool using_guc)
0324 {
0325     struct igt_spinner spin;
0326     struct i915_request *rq;
0327     int err;
0328
0329     err = igt_spinner_init(&spin, ce->engine->gt);
0330     if (err)
0331         return err;
0332
0333     rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
0334     if (IS_ERR(rq)) {
0335         igt_spinner_fini(&spin);
0336         return PTR_ERR(rq);
0337     }
0338
0339     err = request_add_spin(rq, &spin);
0340     if (err == 0 && !using_guc)
0341         err = intel_engine_reset(ce->engine, reason);
0342
0343     /* Ensure the reset happens and kills the engine */
0344     if (err == 0)
0345         err = intel_selftest_wait_for_rq(rq);
0346
0347     igt_spinner_end(&spin);
0348     igt_spinner_fini(&spin);
0349
0350     return err;
0351 }
0352
0353 static int __live_mocs_reset(struct live_mocs *mocs,
0354                  struct intel_context *ce, bool using_guc)
0355 {
0356     struct intel_gt *gt = ce->engine->gt;
0357     int err;
0358
0359     if (intel_has_reset_engine(gt)) {
0360         if (!using_guc) {
0361             err = intel_engine_reset(ce->engine, "mocs");
0362             if (err)
0363                 return err;
0364
0365             err = check_mocs_engine(mocs, ce);
0366             if (err)
0367                 return err;
0368         }
0369
0370         err = active_engine_reset(ce, "mocs", using_guc);
0371         if (err)
0372             return err;
0373
0374         err = check_mocs_engine(mocs, ce);
0375         if (err)
0376             return err;
0377     }
0378
0379     if (intel_has_gpu_reset(gt)) {
0380         intel_gt_reset(gt, ce->engine->mask, "mocs");
0381
0382         err = check_mocs_engine(mocs, ce);
0383         if (err)
0384             return err;
0385     }
0386
0387     return 0;
0388 }
0389
0390 static int live_mocs_reset(void *arg)
0391 {
0392     struct intel_gt *gt = arg;
0393     struct intel_engine_cs *engine;
0394     enum intel_engine_id id;
0395     struct live_mocs mocs;
0396     int err = 0;
0397
0398     /* Check the mocs setup is retained over per-engine and global resets */
0399
0400     err = live_mocs_init(&mocs, gt);
0401     if (err)
0402         return err;
0403
0404     igt_global_reset_lock(gt);
0405     for_each_engine(engine, gt, id) {
0406         bool using_guc = intel_engine_uses_guc(engine);
0407         struct intel_selftest_saved_policy saved;
0408         struct intel_context *ce;
0409         int err2;
0410
0411         err = intel_selftest_modify_policy(engine, &saved,
0412                            SELFTEST_SCHEDULER_MODIFY_FAST_RESET);
0413         if (err)
0414             break;
0415
0416         ce = mocs_context_create(engine);
0417         if (IS_ERR(ce)) {
0418             err = PTR_ERR(ce);
0419             goto restore;
0420         }
0421
0422         intel_engine_pm_get(engine);
0423
0424         err = __live_mocs_reset(&mocs, ce, using_guc);
0425
0426         intel_engine_pm_put(engine);
0427         intel_context_put(ce);
0428
0429 restore:
0430         err2 = intel_selftest_restore_policy(engine, &saved);
0431         if (err == 0)
0432             err = err2;
0433         if (err)
0434             break;
0435     }
0436     igt_global_reset_unlock(gt);
0437
0438     live_mocs_fini(&mocs);
0439     return err;
0440 }
0441
0442 int intel_mocs_live_selftests(struct drm_i915_private *i915)
0443 {
0444     static const struct i915_subtest tests[] = {
0445         SUBTEST(live_mocs_kernel),
0446         SUBTEST(live_mocs_clean),
0447         SUBTEST(live_mocs_reset),
0448     };
0449     struct drm_i915_mocs_table table;
0450
0451     if (!get_mocs_settings(i915, &table))
0452         return 0;
0453
0454     return intel_gt_live_subtests(tests, to_gt(i915));
0455 }