i915/gt/intel_region_lmem.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #include "i915_drv.h"
0007 #include "i915_reg.h"
0008 #include "intel_memory_region.h"
0009 #include "intel_region_lmem.h"
0010 #include "intel_region_ttm.h"
0011 #include "gem/i915_gem_lmem.h"
0012 #include "gem/i915_gem_region.h"
0013 #include "gem/i915_gem_ttm.h"
0014 #include "gt/intel_gt.h"
0015 #include "gt/intel_gt_mcr.h"
0016 #include "gt/intel_gt_regs.h"
0017
0018 #ifdef CONFIG_64BIT
0019 static void _release_bars(struct pci_dev *pdev)
0020 {
0021     int resno;
0022
0023     for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
0024         if (pci_resource_len(pdev, resno))
0025             pci_release_resource(pdev, resno);
0026     }
0027 }
0028
0029 static void
0030 _resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
0031 {
0032     struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
0033     int bar_size = pci_rebar_bytes_to_size(size);
0034     int ret;
0035
0036     _release_bars(pdev);
0037
0038     ret = pci_resize_resource(pdev, resno, bar_size);
0039     if (ret) {
0040         drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
0041              resno, 1 << bar_size, ERR_PTR(ret));
0042         return;
0043     }
0044
0045     drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
0046 }
0047
0048 #define LMEM_BAR_NUM 2
0049 static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size)
0050 {
0051     struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
0052     struct pci_bus *root = pdev->bus;
0053     struct resource *root_res;
0054     resource_size_t rebar_size;
0055     resource_size_t current_size;
0056     u32 pci_cmd;
0057     int i;
0058
0059     current_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
0060
0061     if (i915->params.lmem_bar_size) {
0062         u32 bar_sizes;
0063
0064         rebar_size = i915->params.lmem_bar_size *
0065             (resource_size_t)SZ_1M;
0066         bar_sizes = pci_rebar_get_possible_sizes(pdev,
0067                              LMEM_BAR_NUM);
0068
0069         if (rebar_size == current_size)
0070             return;
0071
0072         if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
0073             rebar_size >= roundup_pow_of_two(lmem_size)) {
0074             rebar_size = lmem_size;
0075
0076             drm_info(&i915->drm,
0077                  "Given bar size is not within supported size, setting it to default: %llu\n",
0078                  (u64)lmem_size >> 20);
0079         }
0080     } else {
0081         rebar_size = current_size;
0082
0083         if (rebar_size != roundup_pow_of_two(lmem_size))
0084             rebar_size = lmem_size;
0085         else
0086             return;
0087     }
0088
0089     /* Find out if root bus contains 64bit memory addressing */
0090     while (root->parent)
0091         root = root->parent;
0092
0093     pci_bus_for_each_resource(root, root_res, i) {
0094         if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
0095             root_res->start > 0x100000000ull)
0096             break;
0097     }
0098
0099     /* pci_resize_resource will fail anyways */
0100     if (!root_res) {
0101         drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
0102         return;
0103     }
0104
0105     /* First disable PCI memory decoding references */
0106     pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
0107     pci_write_config_dword(pdev, PCI_COMMAND,
0108                    pci_cmd & ~PCI_COMMAND_MEMORY);
0109
0110     _resize_bar(i915, LMEM_BAR_NUM, rebar_size);
0111
0112     pci_assign_unassigned_bus_resources(pdev->bus);
0113     pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
0114 }
0115 #else
0116 static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size) {}
0117 #endif
0118
0119 static int
0120 region_lmem_release(struct intel_memory_region *mem)
0121 {
0122     int ret;
0123
0124     ret = intel_region_ttm_fini(mem);
0125     io_mapping_fini(&mem->iomap);
0126
0127     return ret;
0128 }
0129
0130 static int
0131 region_lmem_init(struct intel_memory_region *mem)
0132 {
0133     int ret;
0134
0135     if (!io_mapping_init_wc(&mem->iomap,
0136                 mem->io_start,
0137                 mem->io_size))
0138         return -EIO;
0139
0140     ret = intel_region_ttm_init(mem);
0141     if (ret)
0142         goto out_no_buddy;
0143
0144     return 0;
0145
0146 out_no_buddy:
0147     io_mapping_fini(&mem->iomap);
0148
0149     return ret;
0150 }
0151
0152 static const struct intel_memory_region_ops intel_region_lmem_ops = {
0153     .init = region_lmem_init,
0154     .release = region_lmem_release,
0155     .init_object = __i915_gem_ttm_object_init,
0156 };
0157
0158 static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
0159                      u64 *start, u32 *size)
0160 {
0161     if (!IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0))
0162         return false;
0163
0164     *start = 0;
0165     *size = SZ_1M;
0166
0167     drm_dbg(&uncore->i915->drm, "LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n",
0168         *start, *start + *size);
0169
0170     return true;
0171 }
0172
0173 static int reserve_lowmem_region(struct intel_uncore *uncore,
0174                  struct intel_memory_region *mem)
0175 {
0176     u64 reserve_start;
0177     u32 reserve_size;
0178     int ret;
0179
0180     if (!get_legacy_lowmem_region(uncore, &reserve_start, &reserve_size))
0181         return 0;
0182
0183     ret = intel_memory_region_reserve(mem, reserve_start, reserve_size);
0184     if (ret)
0185         drm_err(&uncore->i915->drm, "LMEM: reserving low memory region failed\n");
0186
0187     return ret;
0188 }
0189
0190 static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
0191 {
0192     struct drm_i915_private *i915 = gt->i915;
0193     struct intel_uncore *uncore = gt->uncore;
0194     struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
0195     struct intel_memory_region *mem;
0196     resource_size_t min_page_size;
0197     resource_size_t io_start;
0198     resource_size_t io_size;
0199     resource_size_t lmem_size;
0200     int err;
0201
0202     if (!IS_DGFX(i915))
0203         return ERR_PTR(-ENODEV);
0204
0205     if (HAS_FLAT_CCS(i915)) {
0206         resource_size_t lmem_range;
0207         u64 tile_stolen, flat_ccs_base;
0208
0209         lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHP_TILE0_ADDR_RANGE) & 0xFFFF;
0210         lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
0211         lmem_size *= SZ_1G;
0212
0213         flat_ccs_base = intel_gt_mcr_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
0214         flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT) * SZ_64K;
0215
0216         if (GEM_WARN_ON(lmem_size < flat_ccs_base))
0217             return ERR_PTR(-EIO);
0218
0219         tile_stolen = lmem_size - flat_ccs_base;
0220
0221         /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an error */
0222         if (tile_stolen == lmem_size)
0223             drm_err(&i915->drm,
0224                 "CCS_BASE_ADDR register did not have expected value\n");
0225
0226         lmem_size -= tile_stolen;
0227     } else {
0228         /* Stolen starts from GSMBASE without CCS */
0229         lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
0230     }
0231
0232     i915_resize_lmem_bar(i915, lmem_size);
0233
0234     if (i915->params.lmem_size > 0) {
0235         lmem_size = min_t(resource_size_t, lmem_size,
0236                   mul_u32_u32(i915->params.lmem_size, SZ_1M));
0237     }
0238
0239     io_start = pci_resource_start(pdev, 2);
0240     io_size = min(pci_resource_len(pdev, 2), lmem_size);
0241     if (!io_size)
0242         return ERR_PTR(-EIO);
0243
0244     min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
0245                         I915_GTT_PAGE_SIZE_4K;
0246     mem = intel_memory_region_create(i915,
0247                      0,
0248                      lmem_size,
0249                      min_page_size,
0250                      io_start,
0251                      io_size,
0252                      INTEL_MEMORY_LOCAL,
0253                      0,
0254                      &intel_region_lmem_ops);
0255     if (IS_ERR(mem))
0256         return mem;
0257
0258     err = reserve_lowmem_region(uncore, mem);
0259     if (err)
0260         goto err_region_put;
0261
0262     drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region);
0263     drm_dbg(&i915->drm, "Local memory IO start: %pa\n",
0264         &mem->io_start);
0265     drm_info(&i915->drm, "Local memory IO size: %pa\n",
0266          &mem->io_size);
0267     drm_info(&i915->drm, "Local memory available: %pa\n",
0268          &lmem_size);
0269
0270     if (io_size < lmem_size)
0271         drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling 'Resizable BAR' or similar, if available in the BIOS.\n",
0272              (u64)io_size >> 20);
0273
0274     return mem;
0275
0276 err_region_put:
0277     intel_memory_region_destroy(mem);
0278     return ERR_PTR(err);
0279 }
0280
0281 struct intel_memory_region *intel_gt_setup_lmem(struct intel_gt *gt)
0282 {
0283     return setup_lmem(gt);
0284 }