i915/gt/intel_lrc_reg.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2014-2018 Intel Corporation
0004  */
0005
0006 #ifndef _INTEL_LRC_REG_H_
0007 #define _INTEL_LRC_REG_H_
0008
0009 #include <linux/types.h>
0010
0011 #define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
0012
0013 /* GEN8 to GEN12 Reg State Context */
0014 #define CTX_CONTEXT_CONTROL     (0x02 + 1)
0015 #define CTX_RING_HEAD           (0x04 + 1)
0016 #define CTX_RING_TAIL           (0x06 + 1)
0017 #define CTX_RING_START          (0x08 + 1)
0018 #define CTX_RING_CTL            (0x0a + 1)
0019 #define CTX_BB_STATE            (0x10 + 1)
0020 #define CTX_TIMESTAMP           (0x22 + 1)
0021 #define CTX_PDP3_UDW            (0x24 + 1)
0022 #define CTX_PDP3_LDW            (0x26 + 1)
0023 #define CTX_PDP2_UDW            (0x28 + 1)
0024 #define CTX_PDP2_LDW            (0x2a + 1)
0025 #define CTX_PDP1_UDW            (0x2c + 1)
0026 #define CTX_PDP1_LDW            (0x2e + 1)
0027 #define CTX_PDP0_UDW            (0x30 + 1)
0028 #define CTX_PDP0_LDW            (0x32 + 1)
0029 #define CTX_R_PWR_CLK_STATE     (0x42 + 1)
0030
0031 #define GEN9_CTX_RING_MI_MODE       0x54
0032
0033 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
0034     u32 *reg_state__ = (reg_state); \
0035     const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \
0036     (reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \
0037     (reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \
0038 } while (0)
0039
0040 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
0041     u32 *reg_state__ = (reg_state); \
0042     const u64 addr__ = px_dma((ppgtt)->pd); \
0043     (reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \
0044     (reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \
0045 } while (0)
0046
0047 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT    0x17
0048 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT    0x26
0049 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0x19
0050 #define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0x1A
0051 #define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0xD
0052
0053 #define GEN8_EXECLISTS_STATUS_BUF 0x370
0054 #define GEN11_EXECLISTS_STATUS_BUF2 0x3c0
0055
0056 /*
0057  * The docs specify that the write pointer wraps around after 5h, "After status
0058  * is written out to the last available status QW at offset 5h, this pointer
0059  * wraps to 0."
0060  *
0061  * Therefore, one must infer than even though there are 3 bits available, 6 and
0062  * 7 appear to be * reserved.
0063  */
0064 #define GEN8_CSB_ENTRIES 6
0065 #define GEN8_CSB_PTR_MASK 0x7
0066 #define GEN8_CSB_READ_PTR_MASK  (GEN8_CSB_PTR_MASK << 8)
0067 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
0068
0069 #define GEN11_CSB_ENTRIES 12
0070 #define GEN11_CSB_PTR_MASK 0xf
0071 #define GEN11_CSB_READ_PTR_MASK     (GEN11_CSB_PTR_MASK << 8)
0072 #define GEN11_CSB_WRITE_PTR_MASK    (GEN11_CSB_PTR_MASK << 0)
0073
0074 #define MAX_CONTEXT_HW_ID   (1 << 21) /* exclusive */
0075 #define GEN11_MAX_CONTEXT_HW_ID (1 << 11) /* exclusive */
0076 /* in Gen12 ID 0x7FF is reserved to indicate idle */
0077 #define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1)
0078 /* in Xe_HP ID 0xFFFF is reserved to indicate "invalid context" */
0079 #define XEHP_MAX_CONTEXT_HW_ID  0xFFFF
0080
0081 #endif /* _INTEL_LRC_REG_H_ */