i915/gt/intel_lrc.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2014 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_LRC_H__
0007 #define __INTEL_LRC_H__
0008
0009 #include "i915_priolist_types.h"
0010
0011 #include <linux/bitfield.h>
0012 #include <linux/types.h>
0013
0014 #include "intel_context.h"
0015
0016 struct drm_i915_gem_object;
0017 struct i915_gem_ww_ctx;
0018 struct intel_engine_cs;
0019 struct intel_ring;
0020 struct kref;
0021
0022 /* At the start of the context image is its per-process HWS page */
0023 #define LRC_PPHWSP_PN   (0)
0024 #define LRC_PPHWSP_SZ   (1)
0025 /* After the PPHWSP we have the logical state for the context */
0026 #define LRC_STATE_PN    (LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
0027 #define LRC_STATE_OFFSET (LRC_STATE_PN * PAGE_SIZE)
0028
0029 /* Space within PPHWSP reserved to be used as scratch */
0030 #define LRC_PPHWSP_SCRATCH      0x34
0031 #define LRC_PPHWSP_SCRATCH_ADDR     (LRC_PPHWSP_SCRATCH * sizeof(u32))
0032
0033 void lrc_init_wa_ctx(struct intel_engine_cs *engine);
0034 void lrc_fini_wa_ctx(struct intel_engine_cs *engine);
0035
0036 int lrc_alloc(struct intel_context *ce,
0037           struct intel_engine_cs *engine);
0038 void lrc_reset(struct intel_context *ce);
0039 void lrc_fini(struct intel_context *ce);
0040 void lrc_destroy(struct kref *kref);
0041
0042 int
0043 lrc_pre_pin(struct intel_context *ce,
0044         struct intel_engine_cs *engine,
0045         struct i915_gem_ww_ctx *ww,
0046         void **vaddr);
0047 int
0048 lrc_pin(struct intel_context *ce,
0049     struct intel_engine_cs *engine,
0050     void *vaddr);
0051 void lrc_unpin(struct intel_context *ce);
0052 void lrc_post_unpin(struct intel_context *ce);
0053
0054 void lrc_init_state(struct intel_context *ce,
0055             struct intel_engine_cs *engine,
0056             void *state);
0057
0058 void lrc_init_regs(const struct intel_context *ce,
0059            const struct intel_engine_cs *engine,
0060            bool clear);
0061 void lrc_reset_regs(const struct intel_context *ce,
0062             const struct intel_engine_cs *engine);
0063
0064 u32 lrc_update_regs(const struct intel_context *ce,
0065             const struct intel_engine_cs *engine,
0066             u32 head);
0067 void lrc_update_offsets(struct intel_context *ce,
0068             struct intel_engine_cs *engine);
0069
0070 void lrc_check_regs(const struct intel_context *ce,
0071             const struct intel_engine_cs *engine,
0072             const char *when);
0073
0074 void lrc_update_runtime(struct intel_context *ce);
0075
0076 enum {
0077     INTEL_ADVANCED_CONTEXT = 0,
0078     INTEL_LEGACY_32B_CONTEXT,
0079     INTEL_ADVANCED_AD_CONTEXT,
0080     INTEL_LEGACY_64B_CONTEXT
0081 };
0082
0083 enum {
0084     FAULT_AND_HANG = 0,
0085     FAULT_AND_HALT, /* Debug only */
0086     FAULT_AND_STREAM,
0087     FAULT_AND_CONTINUE /* Unsupported */
0088 };
0089
0090 #define CTX_GTT_ADDRESS_MASK            GENMASK(31, 12)
0091 #define GEN8_CTX_VALID              (1 << 0)
0092 #define GEN8_CTX_FORCE_PD_RESTORE       (1 << 1)
0093 #define GEN8_CTX_FORCE_RESTORE          (1 << 2)
0094 #define GEN8_CTX_L3LLC_COHERENT         (1 << 5)
0095 #define GEN8_CTX_PRIVILEGE          (1 << 8)
0096 #define GEN8_CTX_ADDRESSING_MODE_SHIFT      3
0097 #define GEN12_CTX_PRIORITY_MASK         GENMASK(10, 9)
0098 #define GEN12_CTX_PRIORITY_HIGH         FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2)
0099 #define GEN12_CTX_PRIORITY_NORMAL       FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1)
0100 #define GEN12_CTX_PRIORITY_LOW          FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0)
0101 #define GEN8_CTX_ID_SHIFT           32
0102 #define GEN8_CTX_ID_WIDTH           21
0103 #define GEN11_SW_CTX_ID_SHIFT           37
0104 #define GEN11_SW_CTX_ID_WIDTH           11
0105 #define GEN11_ENGINE_CLASS_SHIFT        61
0106 #define GEN11_ENGINE_CLASS_WIDTH        3
0107 #define GEN11_ENGINE_INSTANCE_SHIFT     48
0108 #define GEN11_ENGINE_INSTANCE_WIDTH     6
0109 #define XEHP_SW_CTX_ID_SHIFT            39
0110 #define XEHP_SW_CTX_ID_WIDTH            16
0111 #define XEHP_SW_COUNTER_SHIFT           58
0112 #define XEHP_SW_COUNTER_WIDTH           6
0113
0114 static inline void lrc_runtime_start(struct intel_context *ce)
0115 {
0116     struct intel_context_stats *stats = &ce->stats;
0117
0118     if (intel_context_is_barrier(ce))
0119         return;
0120
0121     if (stats->active)
0122         return;
0123
0124     WRITE_ONCE(stats->active, intel_context_clock());
0125 }
0126
0127 static inline void lrc_runtime_stop(struct intel_context *ce)
0128 {
0129     struct intel_context_stats *stats = &ce->stats;
0130
0131     if (!stats->active)
0132         return;
0133
0134     lrc_update_runtime(ce);
0135     WRITE_ONCE(stats->active, 0);
0136 }
0137
0138 #define DG2_PREDICATE_RESULT_WA (PAGE_SIZE - sizeof(u64))
0139 #define DG2_PREDICATE_RESULT_BB (2048)
0140
0141 u32 lrc_indirect_bb(const struct intel_context *ce);
0142
0143 #endif /* __INTEL_LRC_H__ */