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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005 
0006 #include <drm/drm_device.h>
0007 #include <linux/sysfs.h>
0008 #include <linux/printk.h>
0009 
0010 #include "i915_drv.h"
0011 #include "i915_reg.h"
0012 #include "i915_sysfs.h"
0013 #include "intel_gt.h"
0014 #include "intel_gt_regs.h"
0015 #include "intel_gt_sysfs.h"
0016 #include "intel_gt_sysfs_pm.h"
0017 #include "intel_pcode.h"
0018 #include "intel_rc6.h"
0019 #include "intel_rps.h"
0020 
0021 enum intel_gt_sysfs_op {
0022     INTEL_GT_SYSFS_MIN = 0,
0023     INTEL_GT_SYSFS_MAX,
0024 };
0025 
0026 static int
0027 sysfs_gt_attribute_w_func(struct device *dev, struct device_attribute *attr,
0028               int (func)(struct intel_gt *gt, u32 val), u32 val)
0029 {
0030     struct intel_gt *gt;
0031     int ret;
0032 
0033     if (!is_object_gt(&dev->kobj)) {
0034         int i;
0035         struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
0036 
0037         for_each_gt(gt, i915, i) {
0038             ret = func(gt, val);
0039             if (ret)
0040                 break;
0041         }
0042     } else {
0043         gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
0044         ret = func(gt, val);
0045     }
0046 
0047     return ret;
0048 }
0049 
0050 static u32
0051 sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
0052               u32 (func)(struct intel_gt *gt),
0053               enum intel_gt_sysfs_op op)
0054 {
0055     struct intel_gt *gt;
0056     u32 ret;
0057 
0058     ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;
0059 
0060     if (!is_object_gt(&dev->kobj)) {
0061         int i;
0062         struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
0063 
0064         for_each_gt(gt, i915, i) {
0065             u32 val = func(gt);
0066 
0067             switch (op) {
0068             case INTEL_GT_SYSFS_MIN:
0069                 if (val < ret)
0070                     ret = val;
0071                 break;
0072 
0073             case INTEL_GT_SYSFS_MAX:
0074                 if (val > ret)
0075                     ret = val;
0076                 break;
0077             }
0078         }
0079     } else {
0080         gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
0081         ret = func(gt);
0082     }
0083 
0084     return ret;
0085 }
0086 
0087 /* RC6 interfaces will show the minimum RC6 residency value */
0088 #define sysfs_gt_attribute_r_min_func(d, a, f) \
0089         sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
0090 
0091 /* Frequency interfaces will show the maximum frequency value */
0092 #define sysfs_gt_attribute_r_max_func(d, a, f) \
0093         sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
0094 
0095 #ifdef CONFIG_PM
0096 static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
0097 {
0098     intel_wakeref_t wakeref;
0099     u64 res = 0;
0100 
0101     with_intel_runtime_pm(gt->uncore->rpm, wakeref)
0102         res = intel_rc6_residency_us(&gt->rc6, reg);
0103 
0104     return DIV_ROUND_CLOSEST_ULL(res, 1000);
0105 }
0106 
0107 static ssize_t rc6_enable_show(struct device *dev,
0108                    struct device_attribute *attr,
0109                    char *buff)
0110 {
0111     struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
0112     u8 mask = 0;
0113 
0114     if (HAS_RC6(gt->i915))
0115         mask |= BIT(0);
0116     if (HAS_RC6p(gt->i915))
0117         mask |= BIT(1);
0118     if (HAS_RC6pp(gt->i915))
0119         mask |= BIT(2);
0120 
0121     return sysfs_emit(buff, "%x\n", mask);
0122 }
0123 
0124 static u32 __rc6_residency_ms_show(struct intel_gt *gt)
0125 {
0126     return get_residency(gt, GEN6_GT_GFX_RC6);
0127 }
0128 
0129 static ssize_t rc6_residency_ms_show(struct device *dev,
0130                      struct device_attribute *attr,
0131                      char *buff)
0132 {
0133     u32 rc6_residency = sysfs_gt_attribute_r_min_func(dev, attr,
0134                               __rc6_residency_ms_show);
0135 
0136     return sysfs_emit(buff, "%u\n", rc6_residency);
0137 }
0138 
0139 static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
0140 {
0141     return get_residency(gt, GEN6_GT_GFX_RC6p);
0142 }
0143 
0144 static ssize_t rc6p_residency_ms_show(struct device *dev,
0145                       struct device_attribute *attr,
0146                       char *buff)
0147 {
0148     u32 rc6p_residency = sysfs_gt_attribute_r_min_func(dev, attr,
0149                         __rc6p_residency_ms_show);
0150 
0151     return sysfs_emit(buff, "%u\n", rc6p_residency);
0152 }
0153 
0154 static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
0155 {
0156     return get_residency(gt, GEN6_GT_GFX_RC6pp);
0157 }
0158 
0159 static ssize_t rc6pp_residency_ms_show(struct device *dev,
0160                        struct device_attribute *attr,
0161                        char *buff)
0162 {
0163     u32 rc6pp_residency = sysfs_gt_attribute_r_min_func(dev, attr,
0164                         __rc6pp_residency_ms_show);
0165 
0166     return sysfs_emit(buff, "%u\n", rc6pp_residency);
0167 }
0168 
0169 static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
0170 {
0171     return get_residency(gt, VLV_GT_MEDIA_RC6);
0172 }
0173 
0174 static ssize_t media_rc6_residency_ms_show(struct device *dev,
0175                        struct device_attribute *attr,
0176                        char *buff)
0177 {
0178     u32 rc6_residency = sysfs_gt_attribute_r_min_func(dev, attr,
0179                         __media_rc6_residency_ms_show);
0180 
0181     return sysfs_emit(buff, "%u\n", rc6_residency);
0182 }
0183 
0184 static DEVICE_ATTR_RO(rc6_enable);
0185 static DEVICE_ATTR_RO(rc6_residency_ms);
0186 static DEVICE_ATTR_RO(rc6p_residency_ms);
0187 static DEVICE_ATTR_RO(rc6pp_residency_ms);
0188 static DEVICE_ATTR_RO(media_rc6_residency_ms);
0189 
0190 static struct attribute *rc6_attrs[] = {
0191     &dev_attr_rc6_enable.attr,
0192     &dev_attr_rc6_residency_ms.attr,
0193     NULL
0194 };
0195 
0196 static struct attribute *rc6p_attrs[] = {
0197     &dev_attr_rc6p_residency_ms.attr,
0198     &dev_attr_rc6pp_residency_ms.attr,
0199     NULL
0200 };
0201 
0202 static struct attribute *media_rc6_attrs[] = {
0203     &dev_attr_media_rc6_residency_ms.attr,
0204     NULL
0205 };
0206 
0207 static const struct attribute_group rc6_attr_group[] = {
0208     { .attrs = rc6_attrs, },
0209     { .name = power_group_name, .attrs = rc6_attrs, },
0210 };
0211 
0212 static const struct attribute_group rc6p_attr_group[] = {
0213     { .attrs = rc6p_attrs, },
0214     { .name = power_group_name, .attrs = rc6p_attrs, },
0215 };
0216 
0217 static const struct attribute_group media_rc6_attr_group[] = {
0218     { .attrs = media_rc6_attrs, },
0219     { .name = power_group_name, .attrs = media_rc6_attrs, },
0220 };
0221 
0222 static int __intel_gt_sysfs_create_group(struct kobject *kobj,
0223                      const struct attribute_group *grp)
0224 {
0225     return is_object_gt(kobj) ?
0226            sysfs_create_group(kobj, &grp[0]) :
0227            sysfs_merge_group(kobj, &grp[1]);
0228 }
0229 
0230 static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
0231 {
0232     int ret;
0233 
0234     if (!HAS_RC6(gt->i915))
0235         return;
0236 
0237     ret = __intel_gt_sysfs_create_group(kobj, rc6_attr_group);
0238     if (ret)
0239         drm_warn(&gt->i915->drm,
0240              "failed to create gt%u RC6 sysfs files (%pe)\n",
0241              gt->info.id, ERR_PTR(ret));
0242 
0243     /*
0244      * cannot use the is_visible() attribute because
0245      * the upper object inherits from the parent group.
0246      */
0247     if (HAS_RC6p(gt->i915)) {
0248         ret = __intel_gt_sysfs_create_group(kobj, rc6p_attr_group);
0249         if (ret)
0250             drm_warn(&gt->i915->drm,
0251                  "failed to create gt%u RC6p sysfs files (%pe)\n",
0252                  gt->info.id, ERR_PTR(ret));
0253     }
0254 
0255     if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
0256         ret = __intel_gt_sysfs_create_group(kobj, media_rc6_attr_group);
0257         if (ret)
0258             drm_warn(&gt->i915->drm,
0259                  "failed to create media %u RC6 sysfs files (%pe)\n",
0260                  gt->info.id, ERR_PTR(ret));
0261     }
0262 }
0263 #else
0264 static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
0265 {
0266 }
0267 #endif /* CONFIG_PM */
0268 
0269 static u32 __act_freq_mhz_show(struct intel_gt *gt)
0270 {
0271     return intel_rps_read_actual_frequency(&gt->rps);
0272 }
0273 
0274 static ssize_t act_freq_mhz_show(struct device *dev,
0275                  struct device_attribute *attr, char *buff)
0276 {
0277     u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
0278                             __act_freq_mhz_show);
0279 
0280     return sysfs_emit(buff, "%u\n", actual_freq);
0281 }
0282 
0283 static u32 __cur_freq_mhz_show(struct intel_gt *gt)
0284 {
0285     return intel_rps_get_requested_frequency(&gt->rps);
0286 }
0287 
0288 static ssize_t cur_freq_mhz_show(struct device *dev,
0289                  struct device_attribute *attr, char *buff)
0290 {
0291     u32 cur_freq = sysfs_gt_attribute_r_max_func(dev, attr,
0292                          __cur_freq_mhz_show);
0293 
0294     return sysfs_emit(buff, "%u\n", cur_freq);
0295 }
0296 
0297 static u32 __boost_freq_mhz_show(struct intel_gt *gt)
0298 {
0299     return intel_rps_get_boost_frequency(&gt->rps);
0300 }
0301 
0302 static ssize_t boost_freq_mhz_show(struct device *dev,
0303                    struct device_attribute *attr,
0304                    char *buff)
0305 {
0306     u32 boost_freq = sysfs_gt_attribute_r_max_func(dev, attr,
0307                            __boost_freq_mhz_show);
0308 
0309     return sysfs_emit(buff, "%u\n", boost_freq);
0310 }
0311 
0312 static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
0313 {
0314     return intel_rps_set_boost_frequency(&gt->rps, val);
0315 }
0316 
0317 static ssize_t boost_freq_mhz_store(struct device *dev,
0318                     struct device_attribute *attr,
0319                     const char *buff, size_t count)
0320 {
0321     ssize_t ret;
0322     u32 val;
0323 
0324     ret = kstrtou32(buff, 0, &val);
0325     if (ret)
0326         return ret;
0327 
0328     return sysfs_gt_attribute_w_func(dev, attr,
0329                      __boost_freq_mhz_store, val) ?: count;
0330 }
0331 
0332 static u32 __rp0_freq_mhz_show(struct intel_gt *gt)
0333 {
0334     return intel_rps_get_rp0_frequency(&gt->rps);
0335 }
0336 
0337 static ssize_t RP0_freq_mhz_show(struct device *dev,
0338                  struct device_attribute *attr, char *buff)
0339 {
0340     u32 rp0_freq = sysfs_gt_attribute_r_max_func(dev, attr,
0341                              __rp0_freq_mhz_show);
0342 
0343     return sysfs_emit(buff, "%u\n", rp0_freq);
0344 }
0345 
0346 static u32 __rp1_freq_mhz_show(struct intel_gt *gt)
0347 {
0348     return intel_rps_get_rp1_frequency(&gt->rps);
0349 }
0350 
0351 static ssize_t RP1_freq_mhz_show(struct device *dev,
0352                  struct device_attribute *attr, char *buff)
0353 {
0354     u32 rp1_freq = sysfs_gt_attribute_r_max_func(dev, attr,
0355                              __rp1_freq_mhz_show);
0356 
0357     return sysfs_emit(buff, "%u\n", rp1_freq);
0358 }
0359 
0360 static u32 __rpn_freq_mhz_show(struct intel_gt *gt)
0361 {
0362     return intel_rps_get_rpn_frequency(&gt->rps);
0363 }
0364 
0365 static ssize_t RPn_freq_mhz_show(struct device *dev,
0366                  struct device_attribute *attr, char *buff)
0367 {
0368     u32 rpn_freq = sysfs_gt_attribute_r_max_func(dev, attr,
0369                              __rpn_freq_mhz_show);
0370 
0371     return sysfs_emit(buff, "%u\n", rpn_freq);
0372 }
0373 
0374 static u32 __max_freq_mhz_show(struct intel_gt *gt)
0375 {
0376     return intel_rps_get_max_frequency(&gt->rps);
0377 }
0378 
0379 static ssize_t max_freq_mhz_show(struct device *dev,
0380                  struct device_attribute *attr, char *buff)
0381 {
0382     u32 max_freq = sysfs_gt_attribute_r_max_func(dev, attr,
0383                              __max_freq_mhz_show);
0384 
0385     return sysfs_emit(buff, "%u\n", max_freq);
0386 }
0387 
0388 static int __set_max_freq(struct intel_gt *gt, u32 val)
0389 {
0390     return intel_rps_set_max_frequency(&gt->rps, val);
0391 }
0392 
0393 static ssize_t max_freq_mhz_store(struct device *dev,
0394                   struct device_attribute *attr,
0395                   const char *buff, size_t count)
0396 {
0397     int ret;
0398     u32 val;
0399 
0400     ret = kstrtou32(buff, 0, &val);
0401     if (ret)
0402         return ret;
0403 
0404     ret = sysfs_gt_attribute_w_func(dev, attr, __set_max_freq, val);
0405 
0406     return ret ?: count;
0407 }
0408 
0409 static u32 __min_freq_mhz_show(struct intel_gt *gt)
0410 {
0411     return intel_rps_get_min_frequency(&gt->rps);
0412 }
0413 
0414 static ssize_t min_freq_mhz_show(struct device *dev,
0415                  struct device_attribute *attr, char *buff)
0416 {
0417     u32 min_freq = sysfs_gt_attribute_r_min_func(dev, attr,
0418                              __min_freq_mhz_show);
0419 
0420     return sysfs_emit(buff, "%u\n", min_freq);
0421 }
0422 
0423 static int __set_min_freq(struct intel_gt *gt, u32 val)
0424 {
0425     return intel_rps_set_min_frequency(&gt->rps, val);
0426 }
0427 
0428 static ssize_t min_freq_mhz_store(struct device *dev,
0429                   struct device_attribute *attr,
0430                   const char *buff, size_t count)
0431 {
0432     int ret;
0433     u32 val;
0434 
0435     ret = kstrtou32(buff, 0, &val);
0436     if (ret)
0437         return ret;
0438 
0439     ret = sysfs_gt_attribute_w_func(dev, attr, __set_min_freq, val);
0440 
0441     return ret ?: count;
0442 }
0443 
0444 static u32 __vlv_rpe_freq_mhz_show(struct intel_gt *gt)
0445 {
0446     struct intel_rps *rps = &gt->rps;
0447 
0448     return intel_gpu_freq(rps, rps->efficient_freq);
0449 }
0450 
0451 static ssize_t vlv_rpe_freq_mhz_show(struct device *dev,
0452                      struct device_attribute *attr, char *buff)
0453 {
0454     u32 rpe_freq = sysfs_gt_attribute_r_max_func(dev, attr,
0455                          __vlv_rpe_freq_mhz_show);
0456 
0457     return sysfs_emit(buff, "%u\n", rpe_freq);
0458 }
0459 
0460 #define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
0461     static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
0462     static struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
0463 
0464 #define INTEL_GT_RPS_SYSFS_ATTR_RO(_name)               \
0465         INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL)
0466 #define INTEL_GT_RPS_SYSFS_ATTR_RW(_name)               \
0467         INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store)
0468 
0469 /* The below macros generate static structures */
0470 INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
0471 INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
0472 INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
0473 INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
0474 INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
0475 INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
0476 INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
0477 INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
0478 
0479 static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
0480 
0481 #define GEN6_ATTR(s) { \
0482         &dev_attr_##s##_act_freq_mhz.attr, \
0483         &dev_attr_##s##_cur_freq_mhz.attr, \
0484         &dev_attr_##s##_boost_freq_mhz.attr, \
0485         &dev_attr_##s##_max_freq_mhz.attr, \
0486         &dev_attr_##s##_min_freq_mhz.attr, \
0487         &dev_attr_##s##_RP0_freq_mhz.attr, \
0488         &dev_attr_##s##_RP1_freq_mhz.attr, \
0489         &dev_attr_##s##_RPn_freq_mhz.attr, \
0490         NULL, \
0491     }
0492 
0493 #define GEN6_RPS_ATTR GEN6_ATTR(rps)
0494 #define GEN6_GT_ATTR  GEN6_ATTR(gt)
0495 
0496 static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
0497 static const struct attribute * const gen6_gt_attrs[]  = GEN6_GT_ATTR;
0498 
0499 static ssize_t punit_req_freq_mhz_show(struct device *dev,
0500                        struct device_attribute *attr,
0501                        char *buff)
0502 {
0503     struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
0504     u32 preq = intel_rps_read_punit_req_frequency(&gt->rps);
0505 
0506     return sysfs_emit(buff, "%u\n", preq);
0507 }
0508 
0509 struct intel_gt_bool_throttle_attr {
0510     struct attribute attr;
0511     ssize_t (*show)(struct device *dev, struct device_attribute *attr,
0512             char *buf);
0513     i915_reg_t reg32;
0514     u32 mask;
0515 };
0516 
0517 static ssize_t throttle_reason_bool_show(struct device *dev,
0518                      struct device_attribute *attr,
0519                      char *buff)
0520 {
0521     struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
0522     struct intel_gt_bool_throttle_attr *t_attr =
0523                 (struct intel_gt_bool_throttle_attr *) attr;
0524     bool val = rps_read_mask_mmio(&gt->rps, t_attr->reg32, t_attr->mask);
0525 
0526     return sysfs_emit(buff, "%u\n", val);
0527 }
0528 
0529 #define INTEL_GT_RPS_BOOL_ATTR_RO(sysfs_func__, mask__) \
0530 struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
0531     .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
0532     .show = throttle_reason_bool_show, \
0533     .reg32 = GT0_PERF_LIMIT_REASONS, \
0534     .mask = mask__, \
0535 }
0536 
0537 static DEVICE_ATTR_RO(punit_req_freq_mhz);
0538 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
0539 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
0540 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
0541 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl4, POWER_LIMIT_4_MASK);
0542 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_thermal, THERMAL_LIMIT_MASK);
0543 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_prochot, PROCHOT_MASK);
0544 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_ratl, RATL_MASK);
0545 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_thermalert, VR_THERMALERT_MASK);
0546 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_tdc, VR_TDC_MASK);
0547 
0548 static const struct attribute *throttle_reason_attrs[] = {
0549     &attr_throttle_reason_status.attr,
0550     &attr_throttle_reason_pl1.attr,
0551     &attr_throttle_reason_pl2.attr,
0552     &attr_throttle_reason_pl4.attr,
0553     &attr_throttle_reason_thermal.attr,
0554     &attr_throttle_reason_prochot.attr,
0555     &attr_throttle_reason_ratl.attr,
0556     &attr_throttle_reason_vr_thermalert.attr,
0557     &attr_throttle_reason_vr_tdc.attr,
0558     NULL
0559 };
0560 
0561 /*
0562  * Scaling for multipliers (aka frequency factors).
0563  * The format of the value in the register is u8.8.
0564  *
0565  * The presentation to userspace is inspired by the perf event framework.
0566  * See:
0567  *   Documentation/ABI/testing/sysfs-bus-event_source-devices-events
0568  * for description of:
0569  *   /sys/bus/event_source/devices/<pmu>/events/<event>.scale
0570  *
0571  * Summary: Expose two sysfs files for each multiplier.
0572  *
0573  * 1. File <attr> contains a raw hardware value.
0574  * 2. File <attr>.scale contains the multiplicative scale factor to be
0575  *    used by userspace to compute the actual value.
0576  *
0577  * So userspace knows that to get the frequency_factor it multiplies the
0578  * provided value by the specified scale factor and vice-versa.
0579  *
0580  * That way there is no precision loss in the kernel interface and API
0581  * is future proof should one day the hardware register change to u16.u16,
0582  * on some platform. (Or any other fixed point representation.)
0583  *
0584  * Example:
0585  * File <attr> contains the value 2.5, represented as u8.8 0x0280, which
0586  * is comprised of:
0587  * - an integer part of 2
0588  * - a fractional part of 0x80 (representing 0x80 / 2^8 == 0x80 / 256).
0589  * File <attr>.scale contains a string representation of floating point
0590  * value 0.00390625 (which is (1 / 256)).
0591  * Userspace computes the actual value:
0592  *   0x0280 * 0.00390625 -> 2.5
0593  * or converts an actual value to the value to be written into <attr>:
0594  *   2.5 / 0.00390625 -> 0x0280
0595  */
0596 
0597 #define U8_8_VAL_MASK           0xffff
0598 #define U8_8_SCALE_TO_VALUE     "0.00390625"
0599 
0600 static ssize_t freq_factor_scale_show(struct device *dev,
0601                       struct device_attribute *attr,
0602                       char *buff)
0603 {
0604     return sysfs_emit(buff, "%s\n", U8_8_SCALE_TO_VALUE);
0605 }
0606 
0607 static u32 media_ratio_mode_to_factor(u32 mode)
0608 {
0609     /* 0 -> 0, 1 -> 256, 2 -> 128 */
0610     return !mode ? mode : 256 / mode;
0611 }
0612 
0613 static ssize_t media_freq_factor_show(struct device *dev,
0614                       struct device_attribute *attr,
0615                       char *buff)
0616 {
0617     struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
0618     struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
0619     intel_wakeref_t wakeref;
0620     u32 mode;
0621 
0622     /*
0623      * Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
0624      * GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
0625      */
0626     if (IS_XEHPSDV(gt->i915) &&
0627         slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
0628         /*
0629          * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
0630          * the media_ratio_mode, just return the cached media ratio
0631          */
0632         mode = slpc->media_ratio_mode;
0633     } else {
0634         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
0635             mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
0636         mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
0637             SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
0638             SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
0639     }
0640 
0641     return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
0642 }
0643 
0644 static ssize_t media_freq_factor_store(struct device *dev,
0645                        struct device_attribute *attr,
0646                        const char *buff, size_t count)
0647 {
0648     struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
0649     struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
0650     u32 factor, mode;
0651     int err;
0652 
0653     err = kstrtou32(buff, 0, &factor);
0654     if (err)
0655         return err;
0656 
0657     for (mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
0658          mode <= SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO; mode++)
0659         if (factor == media_ratio_mode_to_factor(mode))
0660             break;
0661 
0662     if (mode > SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO)
0663         return -EINVAL;
0664 
0665     err = intel_guc_slpc_set_media_ratio_mode(slpc, mode);
0666     if (!err) {
0667         slpc->media_ratio_mode = mode;
0668         DRM_DEBUG("Set slpc->media_ratio_mode to %d", mode);
0669     }
0670     return err ?: count;
0671 }
0672 
0673 static ssize_t media_RP0_freq_mhz_show(struct device *dev,
0674                        struct device_attribute *attr,
0675                        char *buff)
0676 {
0677     struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
0678     u32 val;
0679     int err;
0680 
0681     err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
0682                    PCODE_MBOX_FC_SC_READ_FUSED_P0,
0683                    PCODE_MBOX_DOMAIN_MEDIAFF, &val);
0684 
0685     if (err)
0686         return err;
0687 
0688     /* Fused media RP0 read from pcode is in units of 50 MHz */
0689     val *= GT_FREQUENCY_MULTIPLIER;
0690 
0691     return sysfs_emit(buff, "%u\n", val);
0692 }
0693 
0694 static ssize_t media_RPn_freq_mhz_show(struct device *dev,
0695                        struct device_attribute *attr,
0696                        char *buff)
0697 {
0698     struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
0699     u32 val;
0700     int err;
0701 
0702     err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
0703                    PCODE_MBOX_FC_SC_READ_FUSED_PN,
0704                    PCODE_MBOX_DOMAIN_MEDIAFF, &val);
0705 
0706     if (err)
0707         return err;
0708 
0709     /* Fused media RPn read from pcode is in units of 50 MHz */
0710     val *= GT_FREQUENCY_MULTIPLIER;
0711 
0712     return sysfs_emit(buff, "%u\n", val);
0713 }
0714 
0715 static DEVICE_ATTR_RW(media_freq_factor);
0716 static struct device_attribute dev_attr_media_freq_factor_scale =
0717     __ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
0718 static DEVICE_ATTR_RO(media_RP0_freq_mhz);
0719 static DEVICE_ATTR_RO(media_RPn_freq_mhz);
0720 
0721 static const struct attribute *media_perf_power_attrs[] = {
0722     &dev_attr_media_freq_factor.attr,
0723     &dev_attr_media_freq_factor_scale.attr,
0724     &dev_attr_media_RP0_freq_mhz.attr,
0725     &dev_attr_media_RPn_freq_mhz.attr,
0726     NULL
0727 };
0728 
0729 static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
0730                 const struct attribute * const *attrs)
0731 {
0732     int ret;
0733 
0734     if (GRAPHICS_VER(gt->i915) < 6)
0735         return 0;
0736 
0737     ret = sysfs_create_files(kobj, attrs);
0738     if (ret)
0739         return ret;
0740 
0741     if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
0742         ret = sysfs_create_file(kobj, &dev_attr_vlv_rpe_freq_mhz.attr);
0743 
0744     return ret;
0745 }
0746 
0747 void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
0748 {
0749     int ret;
0750 
0751     intel_sysfs_rc6_init(gt, kobj);
0752 
0753     ret = is_object_gt(kobj) ?
0754           intel_sysfs_rps_init(gt, kobj, gen6_rps_attrs) :
0755           intel_sysfs_rps_init(gt, kobj, gen6_gt_attrs);
0756     if (ret)
0757         drm_warn(&gt->i915->drm,
0758              "failed to create gt%u RPS sysfs files (%pe)",
0759              gt->info.id, ERR_PTR(ret));
0760 
0761     /* end of the legacy interfaces */
0762     if (!is_object_gt(kobj))
0763         return;
0764 
0765     ret = sysfs_create_file(kobj, &dev_attr_punit_req_freq_mhz.attr);
0766     if (ret)
0767         drm_warn(&gt->i915->drm,
0768              "failed to create gt%u punit_req_freq_mhz sysfs (%pe)",
0769              gt->info.id, ERR_PTR(ret));
0770 
0771     if (GRAPHICS_VER(gt->i915) >= 11) {
0772         ret = sysfs_create_files(kobj, throttle_reason_attrs);
0773         if (ret)
0774             drm_warn(&gt->i915->drm,
0775                  "failed to create gt%u throttle sysfs files (%pe)",
0776                  gt->info.id, ERR_PTR(ret));
0777     }
0778 
0779     if (HAS_MEDIA_RATIO_MODE(gt->i915) && intel_uc_uses_guc_slpc(&gt->uc)) {
0780         ret = sysfs_create_files(kobj, media_perf_power_attrs);
0781         if (ret)
0782             drm_warn(&gt->i915->drm,
0783                  "failed to create gt%u media_perf_power_attrs sysfs (%pe)\n",
0784                  gt->info.id, ERR_PTR(ret));
0785     }
0786 }
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