i915/gt/intel_gt_pm_irq.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #include "i915_drv.h"
0007 #include "i915_reg.h"
0008 #include "intel_gt.h"
0009 #include "intel_gt_irq.h"
0010 #include "intel_gt_pm_irq.h"
0011 #include "intel_gt_regs.h"
0012
0013 static void write_pm_imr(struct intel_gt *gt)
0014 {
0015     struct drm_i915_private *i915 = gt->i915;
0016     struct intel_uncore *uncore = gt->uncore;
0017     u32 mask = gt->pm_imr;
0018     i915_reg_t reg;
0019
0020     if (GRAPHICS_VER(i915) >= 11) {
0021         reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
0022         mask <<= 16; /* pm is in upper half */
0023     } else if (GRAPHICS_VER(i915) >= 8) {
0024         reg = GEN8_GT_IMR(2);
0025     } else {
0026         reg = GEN6_PMIMR;
0027     }
0028
0029     intel_uncore_write(uncore, reg, mask);
0030 }
0031
0032 static void gen6_gt_pm_update_irq(struct intel_gt *gt,
0033                   u32 interrupt_mask,
0034                   u32 enabled_irq_mask)
0035 {
0036     u32 new_val;
0037
0038     WARN_ON(enabled_irq_mask & ~interrupt_mask);
0039
0040     lockdep_assert_held(&gt->irq_lock);
0041
0042     new_val = gt->pm_imr;
0043     new_val &= ~interrupt_mask;
0044     new_val |= ~enabled_irq_mask & interrupt_mask;
0045
0046     if (new_val != gt->pm_imr) {
0047         gt->pm_imr = new_val;
0048         write_pm_imr(gt);
0049     }
0050 }
0051
0052 void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask)
0053 {
0054     gen6_gt_pm_update_irq(gt, mask, mask);
0055 }
0056
0057 void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
0058 {
0059     gen6_gt_pm_update_irq(gt, mask, 0);
0060 }
0061
0062 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
0063 {
0064     struct intel_uncore *uncore = gt->uncore;
0065     i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
0066
0067     lockdep_assert_held(&gt->irq_lock);
0068
0069     intel_uncore_write(uncore, reg, reset_mask);
0070     intel_uncore_write(uncore, reg, reset_mask);
0071     intel_uncore_posting_read(uncore, reg);
0072 }
0073
0074 static void write_pm_ier(struct intel_gt *gt)
0075 {
0076     struct drm_i915_private *i915 = gt->i915;
0077     struct intel_uncore *uncore = gt->uncore;
0078     u32 mask = gt->pm_ier;
0079     i915_reg_t reg;
0080
0081     if (GRAPHICS_VER(i915) >= 11) {
0082         reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
0083         mask <<= 16; /* pm is in upper half */
0084     } else if (GRAPHICS_VER(i915) >= 8) {
0085         reg = GEN8_GT_IER(2);
0086     } else {
0087         reg = GEN6_PMIER;
0088     }
0089
0090     intel_uncore_write(uncore, reg, mask);
0091 }
0092
0093 void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
0094 {
0095     lockdep_assert_held(&gt->irq_lock);
0096
0097     gt->pm_ier |= enable_mask;
0098     write_pm_ier(gt);
0099     gen6_gt_pm_unmask_irq(gt, enable_mask);
0100 }
0101
0102 void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask)
0103 {
0104     lockdep_assert_held(&gt->irq_lock);
0105
0106     gt->pm_ier &= ~disable_mask;
0107     gen6_gt_pm_mask_irq(gt, disable_mask);
0108     write_pm_ier(gt);
0109 }