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0001 // SPDX-License-Identifier: MIT
0002 
0003 /*
0004  * Copyright © 2019 Intel Corporation
0005  */
0006 
0007 #include <linux/seq_file.h>
0008 #include <linux/string_helpers.h>
0009 
0010 #include "i915_drv.h"
0011 #include "i915_reg.h"
0012 #include "intel_gt.h"
0013 #include "intel_gt_clock_utils.h"
0014 #include "intel_gt_debugfs.h"
0015 #include "intel_gt_pm.h"
0016 #include "intel_gt_pm_debugfs.h"
0017 #include "intel_gt_regs.h"
0018 #include "intel_llc.h"
0019 #include "intel_mchbar_regs.h"
0020 #include "intel_pcode.h"
0021 #include "intel_rc6.h"
0022 #include "intel_rps.h"
0023 #include "intel_runtime_pm.h"
0024 #include "intel_uncore.h"
0025 #include "vlv_sideband.h"
0026 
0027 void intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt)
0028 {
0029     atomic_inc(&gt->user_wakeref);
0030     intel_gt_pm_get(gt);
0031     if (GRAPHICS_VER(gt->i915) >= 6)
0032         intel_uncore_forcewake_user_get(gt->uncore);
0033 }
0034 
0035 void intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt)
0036 {
0037     if (GRAPHICS_VER(gt->i915) >= 6)
0038         intel_uncore_forcewake_user_put(gt->uncore);
0039     intel_gt_pm_put(gt);
0040     atomic_dec(&gt->user_wakeref);
0041 }
0042 
0043 static int forcewake_user_open(struct inode *inode, struct file *file)
0044 {
0045     struct intel_gt *gt = inode->i_private;
0046 
0047     intel_gt_pm_debugfs_forcewake_user_open(gt);
0048 
0049     return 0;
0050 }
0051 
0052 static int forcewake_user_release(struct inode *inode, struct file *file)
0053 {
0054     struct intel_gt *gt = inode->i_private;
0055 
0056     intel_gt_pm_debugfs_forcewake_user_release(gt);
0057 
0058     return 0;
0059 }
0060 
0061 static const struct file_operations forcewake_user_fops = {
0062     .owner = THIS_MODULE,
0063     .open = forcewake_user_open,
0064     .release = forcewake_user_release,
0065 };
0066 
0067 static int fw_domains_show(struct seq_file *m, void *data)
0068 {
0069     struct intel_gt *gt = m->private;
0070     struct intel_uncore *uncore = gt->uncore;
0071     struct intel_uncore_forcewake_domain *fw_domain;
0072     unsigned int tmp;
0073 
0074     seq_printf(m, "user.bypass_count = %u\n",
0075            uncore->user_forcewake_count);
0076 
0077     for_each_fw_domain(fw_domain, uncore, tmp)
0078         seq_printf(m, "%s.wake_count = %u\n",
0079                intel_uncore_forcewake_domain_to_str(fw_domain->id),
0080                READ_ONCE(fw_domain->wake_count));
0081 
0082     return 0;
0083 }
0084 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains);
0085 
0086 static void print_rc6_res(struct seq_file *m,
0087               const char *title,
0088               const i915_reg_t reg)
0089 {
0090     struct intel_gt *gt = m->private;
0091     intel_wakeref_t wakeref;
0092 
0093     with_intel_runtime_pm(gt->uncore->rpm, wakeref)
0094         seq_printf(m, "%s %u (%llu us)\n", title,
0095                intel_uncore_read(gt->uncore, reg),
0096                intel_rc6_residency_us(&gt->rc6, reg));
0097 }
0098 
0099 static int vlv_drpc(struct seq_file *m)
0100 {
0101     struct intel_gt *gt = m->private;
0102     struct intel_uncore *uncore = gt->uncore;
0103     u32 rcctl1, pw_status, mt_fwake_req;
0104 
0105     mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
0106     pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
0107     rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
0108 
0109     seq_printf(m, "RC6 Enabled: %s\n",
0110            str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE |
0111                     GEN6_RC_CTL_EI_MODE(1))));
0112     seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
0113     seq_printf(m, "Render Power Well: %s\n",
0114            (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
0115     seq_printf(m, "Media Power Well: %s\n",
0116            (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
0117 
0118     print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6);
0119     print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
0120 
0121     return fw_domains_show(m, NULL);
0122 }
0123 
0124 static int gen6_drpc(struct seq_file *m)
0125 {
0126     struct intel_gt *gt = m->private;
0127     struct drm_i915_private *i915 = gt->i915;
0128     struct intel_uncore *uncore = gt->uncore;
0129     u32 gt_core_status, mt_fwake_req, rcctl1, rc6vids = 0;
0130     u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
0131 
0132     mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
0133     gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
0134 
0135     rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
0136     if (GRAPHICS_VER(i915) >= 9) {
0137         gen9_powergate_enable =
0138             intel_uncore_read(uncore, GEN9_PG_ENABLE);
0139         gen9_powergate_status =
0140             intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
0141     }
0142 
0143     if (GRAPHICS_VER(i915) <= 7)
0144         snb_pcode_read(gt->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
0145 
0146     seq_printf(m, "RC1e Enabled: %s\n",
0147            str_yes_no(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
0148     seq_printf(m, "RC6 Enabled: %s\n",
0149            str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
0150     if (GRAPHICS_VER(i915) >= 9) {
0151         seq_printf(m, "Render Well Gating Enabled: %s\n",
0152                str_yes_no(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
0153         seq_printf(m, "Media Well Gating Enabled: %s\n",
0154                str_yes_no(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
0155     }
0156     seq_printf(m, "Deep RC6 Enabled: %s\n",
0157            str_yes_no(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
0158     seq_printf(m, "Deepest RC6 Enabled: %s\n",
0159            str_yes_no(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
0160     seq_puts(m, "Current RC state: ");
0161     switch (gt_core_status & GEN6_RCn_MASK) {
0162     case GEN6_RC0:
0163         if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
0164             seq_puts(m, "Core Power Down\n");
0165         else
0166             seq_puts(m, "on\n");
0167         break;
0168     case GEN6_RC3:
0169         seq_puts(m, "RC3\n");
0170         break;
0171     case GEN6_RC6:
0172         seq_puts(m, "RC6\n");
0173         break;
0174     case GEN6_RC7:
0175         seq_puts(m, "RC7\n");
0176         break;
0177     default:
0178         seq_puts(m, "Unknown\n");
0179         break;
0180     }
0181 
0182     seq_printf(m, "Core Power Down: %s\n",
0183            str_yes_no(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
0184     seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
0185     if (GRAPHICS_VER(i915) >= 9) {
0186         seq_printf(m, "Render Power Well: %s\n",
0187                (gen9_powergate_status &
0188                 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
0189         seq_printf(m, "Media Power Well: %s\n",
0190                (gen9_powergate_status &
0191                 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
0192     }
0193 
0194     /* Not exactly sure what this is */
0195     print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
0196               GEN6_GT_GFX_RC6_LOCKED);
0197     print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
0198     print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
0199     print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
0200 
0201     if (GRAPHICS_VER(i915) <= 7) {
0202         seq_printf(m, "RC6   voltage: %dmV\n",
0203                GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
0204         seq_printf(m, "RC6+  voltage: %dmV\n",
0205                GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
0206         seq_printf(m, "RC6++ voltage: %dmV\n",
0207                GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
0208     }
0209 
0210     return fw_domains_show(m, NULL);
0211 }
0212 
0213 static int ilk_drpc(struct seq_file *m)
0214 {
0215     struct intel_gt *gt = m->private;
0216     struct intel_uncore *uncore = gt->uncore;
0217     u32 rgvmodectl, rstdbyctl;
0218     u16 crstandvid;
0219 
0220     rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
0221     rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL);
0222     crstandvid = intel_uncore_read16(uncore, CRSTANDVID);
0223 
0224     seq_printf(m, "HD boost: %s\n",
0225            str_yes_no(rgvmodectl & MEMMODE_BOOST_EN));
0226     seq_printf(m, "Boost freq: %d\n",
0227            (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
0228            MEMMODE_BOOST_FREQ_SHIFT);
0229     seq_printf(m, "HW control enabled: %s\n",
0230            str_yes_no(rgvmodectl & MEMMODE_HWIDLE_EN));
0231     seq_printf(m, "SW control enabled: %s\n",
0232            str_yes_no(rgvmodectl & MEMMODE_SWMODE_EN));
0233     seq_printf(m, "Gated voltage change: %s\n",
0234            str_yes_no(rgvmodectl & MEMMODE_RCLK_GATE));
0235     seq_printf(m, "Starting frequency: P%d\n",
0236            (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
0237     seq_printf(m, "Max P-state: P%d\n",
0238            (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
0239     seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
0240     seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
0241     seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
0242     seq_printf(m, "Render standby enabled: %s\n",
0243            str_yes_no(!(rstdbyctl & RCX_SW_EXIT)));
0244     seq_puts(m, "Current RS state: ");
0245     switch (rstdbyctl & RSX_STATUS_MASK) {
0246     case RSX_STATUS_ON:
0247         seq_puts(m, "on\n");
0248         break;
0249     case RSX_STATUS_RC1:
0250         seq_puts(m, "RC1\n");
0251         break;
0252     case RSX_STATUS_RC1E:
0253         seq_puts(m, "RC1E\n");
0254         break;
0255     case RSX_STATUS_RS1:
0256         seq_puts(m, "RS1\n");
0257         break;
0258     case RSX_STATUS_RS2:
0259         seq_puts(m, "RS2 (RC6)\n");
0260         break;
0261     case RSX_STATUS_RS3:
0262         seq_puts(m, "RC3 (RC6+)\n");
0263         break;
0264     default:
0265         seq_puts(m, "unknown\n");
0266         break;
0267     }
0268 
0269     return 0;
0270 }
0271 
0272 static int drpc_show(struct seq_file *m, void *unused)
0273 {
0274     struct intel_gt *gt = m->private;
0275     struct drm_i915_private *i915 = gt->i915;
0276     intel_wakeref_t wakeref;
0277     int err = -ENODEV;
0278 
0279     with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
0280         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
0281             err = vlv_drpc(m);
0282         else if (GRAPHICS_VER(i915) >= 6)
0283             err = gen6_drpc(m);
0284         else
0285             err = ilk_drpc(m);
0286     }
0287 
0288     return err;
0289 }
0290 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc);
0291 
0292 void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
0293 {
0294     struct drm_i915_private *i915 = gt->i915;
0295     struct intel_uncore *uncore = gt->uncore;
0296     struct intel_rps *rps = &gt->rps;
0297     intel_wakeref_t wakeref;
0298 
0299     wakeref = intel_runtime_pm_get(uncore->rpm);
0300 
0301     if (GRAPHICS_VER(i915) == 5) {
0302         u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
0303         u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
0304 
0305         drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
0306         drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f);
0307         drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
0308                MEMSTAT_VID_SHIFT);
0309         drm_printf(p, "Current P-state: %d\n",
0310                (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0311     } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
0312         u32 rpmodectl, freq_sts;
0313 
0314         rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
0315         drm_printf(p, "Video Turbo Mode: %s\n",
0316                str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
0317         drm_printf(p, "HW control enabled: %s\n",
0318                str_yes_no(rpmodectl & GEN6_RP_ENABLE));
0319         drm_printf(p, "SW control enabled: %s\n",
0320                str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
0321 
0322         vlv_punit_get(i915);
0323         freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
0324         vlv_punit_put(i915);
0325 
0326         drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
0327         drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq);
0328 
0329         drm_printf(p, "actual GPU freq: %d MHz\n",
0330                intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
0331 
0332         drm_printf(p, "current GPU freq: %d MHz\n",
0333                intel_gpu_freq(rps, rps->cur_freq));
0334 
0335         drm_printf(p, "max GPU freq: %d MHz\n",
0336                intel_gpu_freq(rps, rps->max_freq));
0337 
0338         drm_printf(p, "min GPU freq: %d MHz\n",
0339                intel_gpu_freq(rps, rps->min_freq));
0340 
0341         drm_printf(p, "idle GPU freq: %d MHz\n",
0342                intel_gpu_freq(rps, rps->idle_freq));
0343 
0344         drm_printf(p, "efficient (RPe) frequency: %d MHz\n",
0345                intel_gpu_freq(rps, rps->efficient_freq));
0346     } else if (GRAPHICS_VER(i915) >= 6) {
0347         u32 rp_state_limits;
0348         u32 gt_perf_status;
0349         struct intel_rps_freq_caps caps;
0350         u32 rpmodectl, rpinclimit, rpdeclimit;
0351         u32 rpstat, cagf, reqf;
0352         u32 rpcurupei, rpcurup, rpprevup;
0353         u32 rpcurdownei, rpcurdown, rpprevdown;
0354         u32 rpupei, rpupt, rpdownei, rpdownt;
0355         u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
0356 
0357         rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
0358         gen6_rps_get_freq_caps(rps, &caps);
0359         if (IS_GEN9_LP(i915))
0360             gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
0361         else
0362             gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
0363 
0364         /* RPSTAT1 is in the GT power well */
0365         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
0366 
0367         reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
0368         if (GRAPHICS_VER(i915) >= 9) {
0369             reqf >>= 23;
0370         } else {
0371             reqf &= ~GEN6_TURBO_DISABLE;
0372             if (IS_HASWELL(i915) || IS_BROADWELL(i915))
0373                 reqf >>= 24;
0374             else
0375                 reqf >>= 25;
0376         }
0377         reqf = intel_gpu_freq(rps, reqf);
0378 
0379         rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
0380         rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
0381         rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
0382 
0383         rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
0384         rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
0385         rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
0386         rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
0387         rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
0388         rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
0389         rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
0390 
0391         rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
0392         rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
0393 
0394         rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
0395         rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
0396 
0397         cagf = intel_rps_read_actual_frequency(rps);
0398 
0399         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
0400 
0401         if (GRAPHICS_VER(i915) >= 11) {
0402             pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
0403             pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
0404             /*
0405              * The equivalent to the PM ISR & IIR cannot be read
0406              * without affecting the current state of the system
0407              */
0408             pm_isr = 0;
0409             pm_iir = 0;
0410         } else if (GRAPHICS_VER(i915) >= 8) {
0411             pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
0412             pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
0413             pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
0414             pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
0415         } else {
0416             pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
0417             pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
0418             pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
0419             pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
0420         }
0421         pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
0422 
0423         drm_printf(p, "Video Turbo Mode: %s\n",
0424                str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
0425         drm_printf(p, "HW control enabled: %s\n",
0426                str_yes_no(rpmodectl & GEN6_RP_ENABLE));
0427         drm_printf(p, "SW control enabled: %s\n",
0428                str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
0429 
0430         drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
0431                pm_ier, pm_imr, pm_mask);
0432         if (GRAPHICS_VER(i915) <= 10)
0433             drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
0434                    pm_isr, pm_iir);
0435         drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
0436                rps->pm_intrmsk_mbz);
0437         drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
0438         drm_printf(p, "Render p-state ratio: %d\n",
0439                (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
0440         drm_printf(p, "Render p-state VID: %d\n",
0441                gt_perf_status & 0xff);
0442         drm_printf(p, "Render p-state limit: %d\n",
0443                rp_state_limits & 0xff);
0444         drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
0445         drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
0446         drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
0447         drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
0448         drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
0449         drm_printf(p, "CAGF: %dMHz\n", cagf);
0450         drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
0451                rpcurupei,
0452                intel_gt_pm_interval_to_ns(gt, rpcurupei));
0453         drm_printf(p, "RP CUR UP: %d (%lldns)\n",
0454                rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
0455         drm_printf(p, "RP PREV UP: %d (%lldns)\n",
0456                rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
0457         drm_printf(p, "Up threshold: %d%%\n",
0458                rps->power.up_threshold);
0459         drm_printf(p, "RP UP EI: %d (%lldns)\n",
0460                rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
0461         drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
0462                rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
0463 
0464         drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
0465                rpcurdownei,
0466                intel_gt_pm_interval_to_ns(gt, rpcurdownei));
0467         drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
0468                rpcurdown,
0469                intel_gt_pm_interval_to_ns(gt, rpcurdown));
0470         drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
0471                rpprevdown,
0472                intel_gt_pm_interval_to_ns(gt, rpprevdown));
0473         drm_printf(p, "Down threshold: %d%%\n",
0474                rps->power.down_threshold);
0475         drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
0476                rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
0477         drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
0478                rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
0479 
0480         drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
0481                intel_gpu_freq(rps, caps.min_freq));
0482         drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
0483                intel_gpu_freq(rps, caps.rp1_freq));
0484         drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
0485                intel_gpu_freq(rps, caps.rp0_freq));
0486         drm_printf(p, "Max overclocked frequency: %dMHz\n",
0487                intel_gpu_freq(rps, rps->max_freq));
0488 
0489         drm_printf(p, "Current freq: %d MHz\n",
0490                intel_gpu_freq(rps, rps->cur_freq));
0491         drm_printf(p, "Actual freq: %d MHz\n", cagf);
0492         drm_printf(p, "Idle freq: %d MHz\n",
0493                intel_gpu_freq(rps, rps->idle_freq));
0494         drm_printf(p, "Min freq: %d MHz\n",
0495                intel_gpu_freq(rps, rps->min_freq));
0496         drm_printf(p, "Boost freq: %d MHz\n",
0497                intel_gpu_freq(rps, rps->boost_freq));
0498         drm_printf(p, "Max freq: %d MHz\n",
0499                intel_gpu_freq(rps, rps->max_freq));
0500         drm_printf(p,
0501                "efficient (RPe) frequency: %d MHz\n",
0502                intel_gpu_freq(rps, rps->efficient_freq));
0503     } else {
0504         drm_puts(p, "no P-state info available\n");
0505     }
0506 
0507     drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
0508     drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);
0509     drm_printf(p, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
0510 
0511     intel_runtime_pm_put(uncore->rpm, wakeref);
0512 }
0513 
0514 static int frequency_show(struct seq_file *m, void *unused)
0515 {
0516     struct intel_gt *gt = m->private;
0517     struct drm_printer p = drm_seq_file_printer(m);
0518 
0519     intel_gt_pm_frequency_dump(gt, &p);
0520 
0521     return 0;
0522 }
0523 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(frequency);
0524 
0525 static int llc_show(struct seq_file *m, void *data)
0526 {
0527     struct intel_gt *gt = m->private;
0528     struct drm_i915_private *i915 = gt->i915;
0529     const bool edram = GRAPHICS_VER(i915) > 8;
0530     struct intel_rps *rps = &gt->rps;
0531     unsigned int max_gpu_freq, min_gpu_freq;
0532     intel_wakeref_t wakeref;
0533     int gpu_freq, ia_freq;
0534 
0535     seq_printf(m, "LLC: %s\n", str_yes_no(HAS_LLC(i915)));
0536     seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
0537            i915->edram_size_mb);
0538 
0539     min_gpu_freq = rps->min_freq;
0540     max_gpu_freq = rps->max_freq;
0541     if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
0542         /* Convert GT frequency to 50 HZ units */
0543         min_gpu_freq /= GEN9_FREQ_SCALER;
0544         max_gpu_freq /= GEN9_FREQ_SCALER;
0545     }
0546 
0547     seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
0548 
0549     wakeref = intel_runtime_pm_get(gt->uncore->rpm);
0550     for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
0551         ia_freq = gpu_freq;
0552         snb_pcode_read(gt->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
0553                    &ia_freq, NULL);
0554         seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
0555                intel_gpu_freq(rps,
0556                       (gpu_freq *
0557                        (IS_GEN9_BC(i915) ||
0558                         GRAPHICS_VER(i915) >= 11 ?
0559                         GEN9_FREQ_SCALER : 1))),
0560                ((ia_freq >> 0) & 0xff) * 100,
0561                ((ia_freq >> 8) & 0xff) * 100);
0562     }
0563     intel_runtime_pm_put(gt->uncore->rpm, wakeref);
0564 
0565     return 0;
0566 }
0567 
0568 static bool llc_eval(void *data)
0569 {
0570     struct intel_gt *gt = data;
0571 
0572     return HAS_LLC(gt->i915);
0573 }
0574 
0575 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(llc);
0576 
0577 static const char *rps_power_to_str(unsigned int power)
0578 {
0579     static const char * const strings[] = {
0580         [LOW_POWER] = "low power",
0581         [BETWEEN] = "mixed",
0582         [HIGH_POWER] = "high power",
0583     };
0584 
0585     if (power >= ARRAY_SIZE(strings) || !strings[power])
0586         return "unknown";
0587 
0588     return strings[power];
0589 }
0590 
0591 static int rps_boost_show(struct seq_file *m, void *data)
0592 {
0593     struct intel_gt *gt = m->private;
0594     struct drm_i915_private *i915 = gt->i915;
0595     struct intel_rps *rps = &gt->rps;
0596 
0597     seq_printf(m, "RPS enabled? %s\n",
0598            str_yes_no(intel_rps_is_enabled(rps)));
0599     seq_printf(m, "RPS active? %s\n",
0600            str_yes_no(intel_rps_is_active(rps)));
0601     seq_printf(m, "GPU busy? %s, %llums\n",
0602            str_yes_no(gt->awake),
0603            ktime_to_ms(intel_gt_get_awake_time(gt)));
0604     seq_printf(m, "Boosts outstanding? %d\n",
0605            atomic_read(&rps->num_waiters));
0606     seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
0607     seq_printf(m, "Frequency requested %d, actual %d\n",
0608            intel_gpu_freq(rps, rps->cur_freq),
0609            intel_rps_read_actual_frequency(rps));
0610     seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
0611            intel_gpu_freq(rps, rps->min_freq),
0612            intel_gpu_freq(rps, rps->min_freq_softlimit),
0613            intel_gpu_freq(rps, rps->max_freq_softlimit),
0614            intel_gpu_freq(rps, rps->max_freq));
0615     seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
0616            intel_gpu_freq(rps, rps->idle_freq),
0617            intel_gpu_freq(rps, rps->efficient_freq),
0618            intel_gpu_freq(rps, rps->boost_freq));
0619 
0620     seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
0621 
0622     if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
0623         struct intel_uncore *uncore = gt->uncore;
0624         u32 rpup, rpupei;
0625         u32 rpdown, rpdownei;
0626 
0627         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
0628         rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
0629         rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
0630         rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
0631         rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
0632         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
0633 
0634         seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
0635                rps_power_to_str(rps->power.mode));
0636         seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
0637                rpup && rpupei ? 100 * rpup / rpupei : 0,
0638                rps->power.up_threshold);
0639         seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
0640                rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
0641                rps->power.down_threshold);
0642     } else {
0643         seq_puts(m, "\nRPS Autotuning inactive\n");
0644     }
0645 
0646     return 0;
0647 }
0648 
0649 static bool rps_eval(void *data)
0650 {
0651     struct intel_gt *gt = data;
0652 
0653     return HAS_RPS(gt->i915);
0654 }
0655 
0656 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
0657 
0658 void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
0659 {
0660     static const struct intel_gt_debugfs_file files[] = {
0661         { "drpc", &drpc_fops, NULL },
0662         { "frequency", &frequency_fops, NULL },
0663         { "forcewake", &fw_domains_fops, NULL },
0664         { "forcewake_user", &forcewake_user_fops, NULL},
0665         { "llc", &llc_fops, llc_eval },
0666         { "rps_boost", &rps_boost_fops, rps_eval },
0667     };
0668 
0669     intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
0670 }
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