i915/gt/intel_gt_mcr.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_GT_MCR__
0007 #define __INTEL_GT_MCR__
0008
0009 #include "intel_gt_types.h"
0010
0011 void intel_gt_mcr_init(struct intel_gt *gt);
0012
0013 u32 intel_gt_mcr_read(struct intel_gt *gt,
0014               i915_reg_t reg,
0015               int group, int instance);
0016 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg);
0017 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg);
0018
0019 void intel_gt_mcr_unicast_write(struct intel_gt *gt,
0020                 i915_reg_t reg, u32 value,
0021                 int group, int instance);
0022 void intel_gt_mcr_multicast_write(struct intel_gt *gt,
0023                   i915_reg_t reg, u32 value);
0024 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt,
0025                      i915_reg_t reg, u32 value);
0026
0027 void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
0028                          i915_reg_t reg,
0029                          u8 *group, u8 *instance);
0030
0031 void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
0032                   bool dump_table);
0033
0034 void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
0035                   unsigned int *group, unsigned int *instance);
0036
0037 /*
0038  * Helper for for_each_ss_steering loop.  On pre-Xe_HP platforms, subslice
0039  * presence is determined by using the group/instance as direct lookups in the
0040  * slice/subslice topology.  On Xe_HP and beyond, the steering is unrelated to
0041  * the topology, so we lookup the DSS ID directly in "slice 0."
0042  */
0043 #define _HAS_SS(ss_, gt_, group_, instance_) ( \
0044     GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \
0045         intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
0046         intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
0047
0048 /*
0049  * Loop over each subslice/DSS and determine the group and instance IDs that
0050  * should be used to steer MCR accesses toward this DSS.
0051  */
0052 #define for_each_ss_steering(ss_, gt_, group_, instance_) \
0053     for (ss_ = 0, intel_gt_mcr_get_ss_steering(gt_, 0, &group_, &instance_); \
0054          ss_ < I915_MAX_SS_FUSE_BITS; \
0055          ss_++, intel_gt_mcr_get_ss_steering(gt_, ss_, &group_, &instance_)) \
0056         for_each_if(_HAS_SS(ss_, gt_, group_, instance_))
0057
0058 #endif /* __INTEL_GT_MCR__ */