i915/gt/intel_gt_irq.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #ifndef INTEL_GT_IRQ_H
0007 #define INTEL_GT_IRQ_H
0008
0009 #include <linux/types.h>
0010
0011 #include "intel_engine_types.h"
0012
0013 struct intel_gt;
0014
0015 #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
0016               GEN8_GT_BCS_IRQ | \
0017               GEN8_GT_VCS0_IRQ | \
0018               GEN8_GT_VCS1_IRQ | \
0019               GEN8_GT_VECS_IRQ | \
0020               GEN8_GT_PM_IRQ | \
0021               GEN8_GT_GUC_IRQ)
0022
0023 void gen11_gt_irq_reset(struct intel_gt *gt);
0024 void gen11_gt_irq_postinstall(struct intel_gt *gt);
0025 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl);
0026
0027 bool gen11_gt_reset_one_iir(struct intel_gt *gt,
0028                 const unsigned int bank,
0029                 const unsigned int bit);
0030
0031 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
0032
0033 void gen5_gt_irq_postinstall(struct intel_gt *gt);
0034 void gen5_gt_irq_reset(struct intel_gt *gt);
0035 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask);
0036 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);
0037
0038 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
0039
0040 void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl);
0041 void gen8_gt_irq_reset(struct intel_gt *gt);
0042 void gen8_gt_irq_postinstall(struct intel_gt *gt);
0043
0044 static inline void intel_engine_cs_irq(struct intel_engine_cs *engine, u16 iir)
0045 {
0046     if (iir)
0047         engine->irq_handler(engine, iir);
0048 }
0049
0050 static inline void
0051 intel_engine_set_irq_handler(struct intel_engine_cs *engine,
0052                  void (*fn)(struct intel_engine_cs *engine,
0053                     u16 iir))
0054 {
0055     /*
0056      * As the interrupt is live as allocate and setup the engines,
0057      * err on the side of caution and apply barriers to updating
0058      * the irq handler callback. This assures that when we do use
0059      * the engine, we will receive interrupts only to ourselves,
0060      * and not lose any.
0061      */
0062     smp_store_mb(engine->irq_handler, fn);
0063 }
0064
0065 #endif /* INTEL_GT_IRQ_H */