i915/gt/intel_gt_debugfs.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #include <linux/debugfs.h>
0007
0008 #include "i915_drv.h"
0009 #include "intel_gt.h"
0010 #include "intel_gt_debugfs.h"
0011 #include "intel_gt_engines_debugfs.h"
0012 #include "intel_gt_mcr.h"
0013 #include "intel_gt_pm_debugfs.h"
0014 #include "intel_sseu_debugfs.h"
0015 #include "pxp/intel_pxp_debugfs.h"
0016 #include "uc/intel_uc_debugfs.h"
0017
0018 int intel_gt_debugfs_reset_show(struct intel_gt *gt, u64 *val)
0019 {
0020     int ret = intel_gt_terminally_wedged(gt);
0021
0022     switch (ret) {
0023     case -EIO:
0024         *val = 1;
0025         return 0;
0026     case 0:
0027         *val = 0;
0028         return 0;
0029     default:
0030         return ret;
0031     }
0032 }
0033
0034 void intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val)
0035 {
0036     /* Flush any previous reset before applying for a new one */
0037     wait_event(gt->reset.queue,
0038            !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
0039
0040     intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
0041                   "Manually reset engine mask to %llx", val);
0042 }
0043
0044 /*
0045  * keep the interface clean where the first parameter
0046  * is a 'struct intel_gt *' instead of 'void *'
0047  */
0048 static int __intel_gt_debugfs_reset_show(void *data, u64 *val)
0049 {
0050     return intel_gt_debugfs_reset_show(data, val);
0051 }
0052
0053 static int __intel_gt_debugfs_reset_store(void *data, u64 val)
0054 {
0055     intel_gt_debugfs_reset_store(data, val);
0056
0057     return 0;
0058 }
0059
0060 DEFINE_SIMPLE_ATTRIBUTE(reset_fops, __intel_gt_debugfs_reset_show,
0061             __intel_gt_debugfs_reset_store, "%llu\n");
0062
0063 static int steering_show(struct seq_file *m, void *data)
0064 {
0065     struct drm_printer p = drm_seq_file_printer(m);
0066     struct intel_gt *gt = m->private;
0067
0068     intel_gt_mcr_report_steering(&p, gt, true);
0069
0070     return 0;
0071 }
0072 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(steering);
0073
0074 static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
0075 {
0076     static const struct intel_gt_debugfs_file files[] = {
0077         { "reset", &reset_fops, NULL },
0078         { "steering", &steering_fops },
0079     };
0080
0081     intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
0082 }
0083
0084 void intel_gt_debugfs_register(struct intel_gt *gt)
0085 {
0086     struct dentry *root;
0087
0088     if (!gt->i915->drm.primary->debugfs_root)
0089         return;
0090
0091     root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
0092     if (IS_ERR(root))
0093         return;
0094
0095     gt_debugfs_register(gt, root);
0096
0097     intel_gt_engines_debugfs_register(gt, root);
0098     intel_gt_pm_debugfs_register(gt, root);
0099     intel_sseu_debugfs_register(gt, root);
0100
0101     intel_uc_debugfs_register(&gt->uc, root);
0102     intel_pxp_debugfs_register(&gt->pxp, root);
0103 }
0104
0105 void intel_gt_debugfs_register_files(struct dentry *root,
0106                      const struct intel_gt_debugfs_file *files,
0107                      unsigned long count, void *data)
0108 {
0109     while (count--) {
0110         umode_t mode = files->fops->write ? 0644 : 0444;
0111
0112         if (!files->eval || files->eval(data))
0113             debugfs_create_file(files->name,
0114                         mode, root, data,
0115                         files->fops);
0116
0117         files++;
0118     }
0119 }