i915/gt/intel_gsc.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
0004  */
0005
0006 #include <linux/irq.h>
0007 #include <linux/mei_aux.h>
0008 #include "i915_drv.h"
0009 #include "i915_reg.h"
0010 #include "gt/intel_gsc.h"
0011 #include "gt/intel_gt.h"
0012
0013 #define GSC_BAR_LENGTH  0x00000FFC
0014
0015 static void gsc_irq_mask(struct irq_data *d)
0016 {
0017     /* generic irq handling */
0018 }
0019
0020 static void gsc_irq_unmask(struct irq_data *d)
0021 {
0022     /* generic irq handling */
0023 }
0024
0025 static struct irq_chip gsc_irq_chip = {
0026     .name = "gsc_irq_chip",
0027     .irq_mask = gsc_irq_mask,
0028     .irq_unmask = gsc_irq_unmask,
0029 };
0030
0031 static int gsc_irq_init(int irq)
0032 {
0033     irq_set_chip_and_handler_name(irq, &gsc_irq_chip,
0034                       handle_simple_irq, "gsc_irq_handler");
0035
0036     return irq_set_chip_data(irq, NULL);
0037 }
0038
0039 struct gsc_def {
0040     const char *name;
0041     unsigned long bar;
0042     size_t bar_size;
0043 };
0044
0045 /* gsc resources and definitions (HECI1 and HECI2) */
0046 static const struct gsc_def gsc_def_dg1[] = {
0047     {
0048         /* HECI1 not yet implemented. */
0049     },
0050     {
0051         .name = "mei-gscfi",
0052         .bar = DG1_GSC_HECI2_BASE,
0053         .bar_size = GSC_BAR_LENGTH,
0054     }
0055 };
0056
0057 static const struct gsc_def gsc_def_dg2[] = {
0058     {
0059         .name = "mei-gsc",
0060         .bar = DG2_GSC_HECI1_BASE,
0061         .bar_size = GSC_BAR_LENGTH,
0062     },
0063     {
0064         .name = "mei-gscfi",
0065         .bar = DG2_GSC_HECI2_BASE,
0066         .bar_size = GSC_BAR_LENGTH,
0067     }
0068 };
0069
0070 static void gsc_release_dev(struct device *dev)
0071 {
0072     struct auxiliary_device *aux_dev = to_auxiliary_dev(dev);
0073     struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
0074
0075     kfree(adev);
0076 }
0077
0078 static void gsc_destroy_one(struct intel_gsc_intf *intf)
0079 {
0080     if (intf->adev) {
0081         auxiliary_device_delete(&intf->adev->aux_dev);
0082         auxiliary_device_uninit(&intf->adev->aux_dev);
0083         intf->adev = NULL;
0084     }
0085     if (intf->irq >= 0)
0086         irq_free_desc(intf->irq);
0087     intf->irq = -1;
0088 }
0089
0090 static void gsc_init_one(struct drm_i915_private *i915,
0091              struct intel_gsc_intf *intf,
0092              unsigned int intf_id)
0093 {
0094     struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
0095     struct mei_aux_device *adev;
0096     struct auxiliary_device *aux_dev;
0097     const struct gsc_def *def;
0098     int ret;
0099
0100     intf->irq = -1;
0101     intf->id = intf_id;
0102
0103     if (intf_id == 0 && !HAS_HECI_PXP(i915))
0104         return;
0105
0106     if (IS_DG1(i915)) {
0107         def = &gsc_def_dg1[intf_id];
0108     } else if (IS_DG2(i915)) {
0109         def = &gsc_def_dg2[intf_id];
0110     } else {
0111         drm_warn_once(&i915->drm, "Unknown platform\n");
0112         return;
0113     }
0114
0115     if (!def->name) {
0116         drm_warn_once(&i915->drm, "HECI%d is not implemented!\n", intf_id + 1);
0117         return;
0118     }
0119
0120     intf->irq = irq_alloc_desc(0);
0121     if (intf->irq < 0) {
0122         drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
0123         return;
0124     }
0125
0126     ret = gsc_irq_init(intf->irq);
0127     if (ret < 0) {
0128         drm_err(&i915->drm, "gsc irq init failed %d\n", ret);
0129         goto fail;
0130     }
0131
0132     adev = kzalloc(sizeof(*adev), GFP_KERNEL);
0133     if (!adev)
0134         goto fail;
0135
0136     adev->irq = intf->irq;
0137     adev->bar.parent = &pdev->resource[0];
0138     adev->bar.start = def->bar + pdev->resource[0].start;
0139     adev->bar.end = adev->bar.start + def->bar_size - 1;
0140     adev->bar.flags = IORESOURCE_MEM;
0141     adev->bar.desc = IORES_DESC_NONE;
0142
0143     aux_dev = &adev->aux_dev;
0144     aux_dev->name = def->name;
0145     aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
0146               PCI_DEVID(pdev->bus->number, pdev->devfn);
0147     aux_dev->dev.parent = &pdev->dev;
0148     aux_dev->dev.release = gsc_release_dev;
0149
0150     ret = auxiliary_device_init(aux_dev);
0151     if (ret < 0) {
0152         drm_err(&i915->drm, "gsc aux init failed %d\n", ret);
0153         kfree(adev);
0154         goto fail;
0155     }
0156
0157     ret = auxiliary_device_add(aux_dev);
0158     if (ret < 0) {
0159         drm_err(&i915->drm, "gsc aux add failed %d\n", ret);
0160         /* adev will be freed with the put_device() and .release sequence */
0161         auxiliary_device_uninit(aux_dev);
0162         goto fail;
0163     }
0164     intf->adev = adev;
0165
0166     return;
0167 fail:
0168     gsc_destroy_one(intf);
0169 }
0170
0171 static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
0172 {
0173     int ret;
0174
0175     if (intf_id >= INTEL_GSC_NUM_INTERFACES) {
0176         drm_warn_once(&gt->i915->drm, "GSC irq: intf_id %d is out of range", intf_id);
0177         return;
0178     }
0179
0180     if (!HAS_HECI_GSC(gt->i915)) {
0181         drm_warn_once(&gt->i915->drm, "GSC irq: not supported");
0182         return;
0183     }
0184
0185     if (gt->gsc.intf[intf_id].irq < 0) {
0186         drm_err_ratelimited(&gt->i915->drm, "GSC irq: irq not set");
0187         return;
0188     }
0189
0190     ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
0191     if (ret)
0192         drm_err_ratelimited(&gt->i915->drm, "error handling GSC irq: %d\n", ret);
0193 }
0194
0195 void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir)
0196 {
0197     if (iir & GSC_IRQ_INTF(0))
0198         gsc_irq_handler(gt, 0);
0199     if (iir & GSC_IRQ_INTF(1))
0200         gsc_irq_handler(gt, 1);
0201 }
0202
0203 void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915)
0204 {
0205     unsigned int i;
0206
0207     if (!HAS_HECI_GSC(i915))
0208         return;
0209
0210     for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
0211         gsc_init_one(i915, &gsc->intf[i], i);
0212 }
0213
0214 void intel_gsc_fini(struct intel_gsc *gsc)
0215 {
0216     struct intel_gt *gt = gsc_to_gt(gsc);
0217     unsigned int i;
0218
0219     if (!HAS_HECI_GSC(gt->i915))
0220         return;
0221
0222     for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
0223         gsc_destroy_one(&gsc->intf[i]);
0224 }