i915/gt/intel_ggtt_fencing.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2016 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_GGTT_FENCING_H__
0007 #define __INTEL_GGTT_FENCING_H__
0008
0009 #include <linux/list.h>
0010 #include <linux/types.h>
0011
0012 #include "i915_active.h"
0013
0014 struct drm_i915_gem_object;
0015 struct i915_ggtt;
0016 struct i915_vma;
0017 struct intel_gt;
0018 struct sg_table;
0019
0020 #define I965_FENCE_PAGE 4096UL
0021
0022 struct i915_fence_reg {
0023     struct list_head link;
0024     struct i915_ggtt *ggtt;
0025     struct i915_vma *vma;
0026     atomic_t pin_count;
0027     struct i915_active active;
0028     int id;
0029     /**
0030      * Whether the tiling parameters for the currently
0031      * associated fence register have changed. Note that
0032      * for the purposes of tracking tiling changes we also
0033      * treat the unfenced register, the register slot that
0034      * the object occupies whilst it executes a fenced
0035      * command (such as BLT on gen2/3), as a "fence".
0036      */
0037     bool dirty;
0038     u32 start;
0039     u32 size;
0040     u32 tiling;
0041     u32 stride;
0042 };
0043
0044 struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt);
0045 void i915_unreserve_fence(struct i915_fence_reg *fence);
0046
0047 void intel_ggtt_restore_fences(struct i915_ggtt *ggtt);
0048
0049 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
0050                        struct sg_table *pages);
0051 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
0052                      struct sg_table *pages);
0053
0054 void intel_ggtt_init_fences(struct i915_ggtt *ggtt);
0055 void intel_ggtt_fini_fences(struct i915_ggtt *ggtt);
0056
0057 void intel_gt_init_swizzling(struct intel_gt *gt);
0058
0059 #endif