i915/gt/intel_engine_regs.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_ENGINE_REGS__
0007 #define __INTEL_ENGINE_REGS__
0008
0009 #include "i915_reg_defs.h"
0010
0011 #define RING_EXCC(base)             _MMIO((base) + 0x28)
0012 #define RING_TAIL(base)             _MMIO((base) + 0x30)
0013 #define   TAIL_ADDR             0x001FFFF8
0014 #define RING_HEAD(base)             _MMIO((base) + 0x34)
0015 #define   HEAD_WRAP_COUNT           0xFFE00000
0016 #define   HEAD_WRAP_ONE             0x00200000
0017 #define   HEAD_ADDR             0x001FFFFC
0018 #define RING_START(base)            _MMIO((base) + 0x38)
0019 #define RING_CTL(base)              _MMIO((base) + 0x3c)
0020 #define   RING_CTL_SIZE(size)           ((size) - PAGE_SIZE) /* in bytes -> pages */
0021 #define   RING_NR_PAGES             0x001FF000
0022 #define   RING_REPORT_MASK          0x00000006
0023 #define   RING_REPORT_64K           0x00000002
0024 #define   RING_REPORT_128K          0x00000004
0025 #define   RING_NO_REPORT            0x00000000
0026 #define   RING_VALID_MASK           0x00000001
0027 #define   RING_VALID                0x00000001
0028 #define   RING_INVALID              0x00000000
0029 #define   RING_WAIT_I8XX            (1 << 0) /* gen2, PRBx_HEAD */
0030 #define   RING_WAIT             (1 << 11) /* gen3+, PRBx_CTL */
0031 #define   RING_WAIT_SEMAPHORE           (1 << 10) /* gen6+ */
0032 #define RING_SYNC_0(base)           _MMIO((base) + 0x40)
0033 #define RING_SYNC_1(base)           _MMIO((base) + 0x44)
0034 #define RING_SYNC_2(base)           _MMIO((base) + 0x48)
0035 #define GEN6_RVSYNC             (RING_SYNC_0(RENDER_RING_BASE))
0036 #define GEN6_RBSYNC             (RING_SYNC_1(RENDER_RING_BASE))
0037 #define GEN6_RVESYNC                (RING_SYNC_2(RENDER_RING_BASE))
0038 #define GEN6_VBSYNC             (RING_SYNC_0(GEN6_BSD_RING_BASE))
0039 #define GEN6_VRSYNC             (RING_SYNC_1(GEN6_BSD_RING_BASE))
0040 #define GEN6_VVESYNC                (RING_SYNC_2(GEN6_BSD_RING_BASE))
0041 #define GEN6_BRSYNC             (RING_SYNC_0(BLT_RING_BASE))
0042 #define GEN6_BVSYNC             (RING_SYNC_1(BLT_RING_BASE))
0043 #define GEN6_BVESYNC                (RING_SYNC_2(BLT_RING_BASE))
0044 #define GEN6_VEBSYNC                (RING_SYNC_0(VEBOX_RING_BASE))
0045 #define GEN6_VERSYNC                (RING_SYNC_1(VEBOX_RING_BASE))
0046 #define GEN6_VEVSYNC                (RING_SYNC_2(VEBOX_RING_BASE))
0047 #define RING_PSMI_CTL(base)         _MMIO((base) + 0x50)
0048 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE     REG_BIT(12)
0049 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE    REG_BIT(10)
0050 #define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
0051 #define   GEN6_BSD_GO_INDICATOR         REG_BIT(4)
0052 #define   GEN6_BSD_SLEEP_INDICATOR      REG_BIT(3)
0053 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE      REG_BIT(2)
0054 #define   GEN6_PSMI_SLEEP_MSG_DISABLE       REG_BIT(0)
0055 #define RING_MAX_IDLE(base)         _MMIO((base) + 0x54)
0056 #define  PWRCTX_MAXCNT(base)            _MMIO((base) + 0x54)
0057 #define    IDLE_TIME_MASK           0xFFFFF
0058 #define RING_ACTHD_UDW(base)            _MMIO((base) + 0x5c)
0059 #define RING_DMA_FADD_UDW(base)         _MMIO((base) + 0x60) /* gen8+ */
0060 #define RING_IPEIR(base)            _MMIO((base) + 0x64)
0061 #define RING_IPEHR(base)            _MMIO((base) + 0x68)
0062 #define RING_INSTDONE(base)         _MMIO((base) + 0x6c)
0063 #define RING_INSTPS(base)           _MMIO((base) + 0x70)
0064 #define RING_DMA_FADD(base)         _MMIO((base) + 0x78)
0065 #define RING_ACTHD(base)            _MMIO((base) + 0x74)
0066 #define RING_HWS_PGA(base)          _MMIO((base) + 0x80)
0067 #define RING_CMD_BUF_CCTL(base)         _MMIO((base) + 0x84)
0068 #define IPEIR(base)             _MMIO((base) + 0x88)
0069 #define IPEHR(base)             _MMIO((base) + 0x8c)
0070 #define RING_ID(base)               _MMIO((base) + 0x8c)
0071 #define RING_NOPID(base)            _MMIO((base) + 0x94)
0072 #define RING_HWSTAM(base)           _MMIO((base) + 0x98)
0073 #define RING_MI_MODE(base)          _MMIO((base) + 0x9c)
0074 #define   ASYNC_FLIP_PERF_DISABLE       REG_BIT(14)
0075 #define   MI_FLUSH_ENABLE           REG_BIT(12)
0076 #define   TGL_NESTED_BB_EN          REG_BIT(12)
0077 #define   MODE_IDLE             REG_BIT(9)
0078 #define   STOP_RING             REG_BIT(8)
0079 #define   VS_TIMER_DISPATCH         REG_BIT(6)
0080 #define RING_IMR(base)              _MMIO((base) + 0xa8)
0081 #define RING_EIR(base)              _MMIO((base) + 0xb0)
0082 #define RING_EMR(base)              _MMIO((base) + 0xb4)
0083 #define RING_ESR(base)              _MMIO((base) + 0xb8)
0084 #define RING_INSTPM(base)           _MMIO((base) + 0xc0)
0085 #define RING_CMD_CCTL(base)         _MMIO((base) + 0xc4)
0086 #define ACTHD(base)             _MMIO((base) + 0xc8)
0087 #define GEN8_R_PWR_CLK_STATE(base)      _MMIO((base) + 0xc8)
0088 #define   GEN8_RPCS_ENABLE          (1 << 31)
0089 #define   GEN8_RPCS_S_CNT_ENABLE        (1 << 18)
0090 #define   GEN8_RPCS_S_CNT_SHIFT         15
0091 #define   GEN8_RPCS_S_CNT_MASK          (0x7 << GEN8_RPCS_S_CNT_SHIFT)
0092 #define   GEN11_RPCS_S_CNT_SHIFT        12
0093 #define   GEN11_RPCS_S_CNT_MASK         (0x3f << GEN11_RPCS_S_CNT_SHIFT)
0094 #define   GEN8_RPCS_SS_CNT_ENABLE       (1 << 11)
0095 #define   GEN8_RPCS_SS_CNT_SHIFT        8
0096 #define   GEN8_RPCS_SS_CNT_MASK         (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
0097 #define   GEN8_RPCS_EU_MAX_SHIFT        4
0098 #define   GEN8_RPCS_EU_MAX_MASK         (0xf << GEN8_RPCS_EU_MAX_SHIFT)
0099 #define   GEN8_RPCS_EU_MIN_SHIFT        0
0100 #define   GEN8_RPCS_EU_MIN_MASK         (0xf << GEN8_RPCS_EU_MIN_SHIFT)
0101
0102 #define RING_RESET_CTL(base)            _MMIO((base) + 0xd0)
0103 #define   RESET_CTL_CAT_ERROR           REG_BIT(2)
0104 #define   RESET_CTL_READY_TO_RESET      REG_BIT(1)
0105 #define   RESET_CTL_REQUEST_RESET       REG_BIT(0)
0106 #define DMA_FADD_I8XX(base)         _MMIO((base) + 0xd0)
0107 #define RING_BBSTATE(base)          _MMIO((base) + 0x110)
0108 #define   RING_BB_PPGTT             (1 << 5)
0109 #define RING_SBBADDR(base)          _MMIO((base) + 0x114) /* hsw+ */
0110 #define RING_SBBSTATE(base)         _MMIO((base) + 0x118) /* hsw+ */
0111 #define RING_SBBADDR_UDW(base)          _MMIO((base) + 0x11c) /* gen8+ */
0112 #define RING_BBADDR(base)           _MMIO((base) + 0x140)
0113 #define RING_BBADDR_UDW(base)           _MMIO((base) + 0x168) /* gen8+ */
0114 #define CCID(base)              _MMIO((base) + 0x180)
0115 #define   CCID_EN               BIT(0)
0116 #define   CCID_EXTENDED_STATE_RESTORE       BIT(2)
0117 #define   CCID_EXTENDED_STATE_SAVE      BIT(3)
0118 #define RING_BB_PER_CTX_PTR(base)       _MMIO((base) + 0x1c0) /* gen8+ */
0119 #define RING_INDIRECT_CTX(base)         _MMIO((base) + 0x1c4) /* gen8+ */
0120 #define RING_INDIRECT_CTX_OFFSET(base)      _MMIO((base) + 0x1c8) /* gen8+ */
0121 #define ECOSKPD(base)               _MMIO((base) + 0x1d0)
0122 #define   ECO_CONSTANT_BUFFER_SR_DISABLE    REG_BIT(4)
0123 #define   ECO_GATING_CX_ONLY            REG_BIT(3)
0124 #define   GEN6_BLITTER_FBC_NOTIFY       REG_BIT(3)
0125 #define   ECO_FLIP_DONE             REG_BIT(0)
0126 #define   GEN6_BLITTER_LOCK_SHIFT       16
0127
0128 #define BLIT_CCTL(base)             _MMIO((base) + 0x204)
0129 #define   BLIT_CCTL_DST_MOCS_MASK       REG_GENMASK(14, 8)
0130 #define   BLIT_CCTL_SRC_MOCS_MASK       REG_GENMASK(6, 0)
0131 #define   BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
0132               BLIT_CCTL_SRC_MOCS_MASK)
0133 #define   BLIT_CCTL_MOCS(dst, src)                     \
0134         (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
0135          REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
0136
0137 #define RING_CSCMDOP(base)          _MMIO((base) + 0x20c)
0138
0139 /*
0140  * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
0141  * The lsb of each can be considered a separate enabling bit for encryption.
0142  * 6:0 == default MOCS value for reads  =>  6:1 == table index for reads.
0143  * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
0144  * 15:14 == Reserved => 31:30 are set to 0.
0145  */
0146 #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
0147 #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
0148 #define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
0149                 CMD_CCTL_READ_OVERRIDE_MASK)
0150 #define CMD_CCTL_MOCS_OVERRIDE(write, read)                   \
0151         (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
0152          REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
0153
0154 #define RING_PREDICATE_RESULT(base)     _MMIO((base) + 0x3b8) /* gen12+ */
0155
0156 #define MI_PREDICATE_RESULT_2(base)     _MMIO((base) + 0x3bc)
0157 #define   LOWER_SLICE_ENABLED           (1 << 0)
0158 #define   LOWER_SLICE_DISABLED          (0 << 0)
0159 #define MI_PREDICATE_SRC0(base)         _MMIO((base) + 0x400)
0160 #define MI_PREDICATE_SRC0_UDW(base)     _MMIO((base) + 0x400 + 4)
0161 #define MI_PREDICATE_SRC1(base)         _MMIO((base) + 0x408)
0162 #define MI_PREDICATE_SRC1_UDW(base)     _MMIO((base) + 0x408 + 4)
0163 #define MI_PREDICATE_DATA(base)         _MMIO((base) + 0x410)
0164 #define MI_PREDICATE_RESULT(base)       _MMIO((base) + 0x418)
0165 #define MI_PREDICATE_RESULT_1(base)     _MMIO((base) + 0x41c)
0166
0167 #define RING_PP_DIR_DCLV(base)          _MMIO((base) + 0x220)
0168 #define   PP_DIR_DCLV_2G            0xffffffff
0169 #define RING_PP_DIR_BASE(base)          _MMIO((base) + 0x228)
0170 #define RING_ELSP(base)             _MMIO((base) + 0x230)
0171 #define RING_EXECLIST_STATUS_LO(base)       _MMIO((base) + 0x234)
0172 #define RING_EXECLIST_STATUS_HI(base)       _MMIO((base) + 0x234 + 4)
0173 #define RING_CONTEXT_CONTROL(base)      _MMIO((base) + 0x244)
0174 #define   CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   REG_BIT(0)
0175 #define   CTX_CTRL_RS_CTX_ENABLE        REG_BIT(1)
0176 #define   CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT  REG_BIT(2)
0177 #define   CTX_CTRL_INHIBIT_SYN_CTX_SWITCH   REG_BIT(3)
0178 #define   GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
0179 #define RING_CTX_SR_CTL(base)           _MMIO((base) + 0x244)
0180 #define RING_SEMA_WAIT_POLL(base)       _MMIO((base) + 0x24c)
0181 #define GEN8_RING_PDP_UDW(base, n)      _MMIO((base) + 0x270 + (n) * 8 + 4)
0182 #define GEN8_RING_PDP_LDW(base, n)      _MMIO((base) + 0x270 + (n) * 8)
0183 #define RING_MODE_GEN7(base)            _MMIO((base) + 0x29c)
0184 #define   GFX_RUN_LIST_ENABLE           (1 << 15)
0185 #define   GFX_INTERRUPT_STEERING        (1 << 14)
0186 #define   GFX_TLB_INVALIDATE_EXPLICIT       (1 << 13)
0187 #define   GFX_SURFACE_FAULT_ENABLE      (1 << 12)
0188 #define   GFX_REPLAY_MODE           (1 << 11)
0189 #define   GFX_PSMI_GRANULARITY          (1 << 10)
0190 #define   GEN12_GFX_PREFETCH_DISABLE        REG_BIT(10)
0191 #define   GFX_PPGTT_ENABLE          (1 << 9)
0192 #define   GEN8_GFX_PPGTT_48B            (1 << 7)
0193 #define   GFX_FORWARD_VBLANK_MASK       (3 << 5)
0194 #define   GFX_FORWARD_VBLANK_NEVER      (0 << 5)
0195 #define   GFX_FORWARD_VBLANK_ALWAYS     (1 << 5)
0196 #define   GFX_FORWARD_VBLANK_COND       (2 << 5)
0197 #define   GEN11_GFX_DISABLE_LEGACY_MODE     (1 << 3)
0198 #define RING_TIMESTAMP(base)            _MMIO((base) + 0x358)
0199 #define RING_TIMESTAMP_UDW(base)        _MMIO((base) + 0x358 + 4)
0200 #define RING_CONTEXT_STATUS_PTR(base)       _MMIO((base) + 0x3a0)
0201 #define RING_CTX_TIMESTAMP(base)        _MMIO((base) + 0x3a8) /* gen8+ */
0202 #define RING_PREDICATE_RESULT(base)     _MMIO((base) + 0x3b8)
0203 #define RING_FORCE_TO_NONPRIV(base, i)      _MMIO(((base) + 0x4D0) + (i) * 4)
0204 #define   RING_FORCE_TO_NONPRIV_DENY        REG_BIT(30)
0205 #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK    REG_GENMASK(25, 2)
0206 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW   (0 << 28)    /* CFL+ & Gen11+ */
0207 #define   RING_FORCE_TO_NONPRIV_ACCESS_RD   (1 << 28)
0208 #define   RING_FORCE_TO_NONPRIV_ACCESS_WR   (2 << 28)
0209 #define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID  (3 << 28)
0210 #define   RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
0211 #define   RING_FORCE_TO_NONPRIV_RANGE_1     (0 << 0)     /* CFL+ & Gen11+ */
0212 #define   RING_FORCE_TO_NONPRIV_RANGE_4     (1 << 0)
0213 #define   RING_FORCE_TO_NONPRIV_RANGE_16    (2 << 0)
0214 #define   RING_FORCE_TO_NONPRIV_RANGE_64    (3 << 0)
0215 #define   RING_FORCE_TO_NONPRIV_RANGE_MASK  (3 << 0)
0216 #define   RING_FORCE_TO_NONPRIV_MASK_VALID  \
0217     (RING_FORCE_TO_NONPRIV_RANGE_MASK | \
0218      RING_FORCE_TO_NONPRIV_ACCESS_MASK | \
0219      RING_FORCE_TO_NONPRIV_DENY)
0220 #define   RING_MAX_NONPRIV_SLOTS  12
0221
0222 #define RING_EXECLIST_SQ_CONTENTS(base)     _MMIO((base) + 0x510)
0223 #define RING_PP_DIR_BASE_READ(base)     _MMIO((base) + 0x518)
0224 #define RING_EXECLIST_CONTROL(base)     _MMIO((base) + 0x550)
0225 #define   EL_CTRL_LOAD              REG_BIT(0)
0226
0227 /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
0228 #define GEN8_RING_CS_GPR(base, n)       _MMIO((base) + 0x600 + (n) * 8)
0229 #define GEN8_RING_CS_GPR_UDW(base, n)       _MMIO((base) + 0x600 + (n) * 8 + 4)
0230
0231 #define GEN11_VCS_SFC_FORCED_LOCK(base)     _MMIO((base) + 0x88c)
0232 #define   GEN11_VCS_SFC_FORCED_LOCK_BIT     (1 << 0)
0233 #define GEN11_VCS_SFC_LOCK_STATUS(base)     _MMIO((base) + 0x890)
0234 #define   GEN11_VCS_SFC_USAGE_BIT       (1 << 0)
0235 #define   GEN11_VCS_SFC_LOCK_ACK_BIT        (1 << 1)
0236
0237 #define GEN11_VECS_SFC_FORCED_LOCK(base)    _MMIO((base) + 0x201c)
0238 #define   GEN11_VECS_SFC_FORCED_LOCK_BIT    (1 << 0)
0239 #define GEN11_VECS_SFC_LOCK_ACK(base)       _MMIO((base) + 0x2018)
0240 #define   GEN11_VECS_SFC_LOCK_ACK_BIT       (1 << 0)
0241 #define GEN11_VECS_SFC_USAGE(base)      _MMIO((base) + 0x2014)
0242 #define   GEN11_VECS_SFC_USAGE_BIT      (1 << 0)
0243
0244 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
0245
0246 #define GEN12_HCP_SFC_LOCK_STATUS(base)     _MMIO((base) + 0x2914)
0247 #define   GEN12_HCP_SFC_LOCK_ACK_BIT        REG_BIT(1)
0248 #define   GEN12_HCP_SFC_USAGE_BIT       REG_BIT(0)
0249
0250 #define VDBOX_CGCTL3F10(base)           _MMIO((base) + 0x3f10)
0251 #define   IECPUNIT_CLKGATE_DIS          REG_BIT(22)
0252
0253 #define VDBOX_CGCTL3F18(base)           _MMIO((base) + 0x3f18)
0254 #define   ALNUNIT_CLKGATE_DIS           REG_BIT(13)
0255
0256
0257 #endif /* __INTEL_ENGINE_REGS__ */