i915/gt/intel_engine_pm.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #include "i915_drv.h"
0007
0008 #include "intel_breadcrumbs.h"
0009 #include "intel_context.h"
0010 #include "intel_engine.h"
0011 #include "intel_engine_heartbeat.h"
0012 #include "intel_engine_pm.h"
0013 #include "intel_gt.h"
0014 #include "intel_gt_pm.h"
0015 #include "intel_rc6.h"
0016 #include "intel_ring.h"
0017 #include "shmem_utils.h"
0018
0019 static void dbg_poison_ce(struct intel_context *ce)
0020 {
0021     if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
0022         return;
0023
0024     if (ce->state) {
0025         struct drm_i915_gem_object *obj = ce->state->obj;
0026         int type = i915_coherent_map_type(ce->engine->i915, obj, true);
0027         void *map;
0028
0029         if (!i915_gem_object_trylock(obj, NULL))
0030             return;
0031
0032         map = i915_gem_object_pin_map(obj, type);
0033         if (!IS_ERR(map)) {
0034             memset(map, CONTEXT_REDZONE, obj->base.size);
0035             i915_gem_object_flush_map(obj);
0036             i915_gem_object_unpin_map(obj);
0037         }
0038         i915_gem_object_unlock(obj);
0039     }
0040 }
0041
0042 static int __engine_unpark(struct intel_wakeref *wf)
0043 {
0044     struct intel_engine_cs *engine =
0045         container_of(wf, typeof(*engine), wakeref);
0046     struct intel_context *ce;
0047
0048     ENGINE_TRACE(engine, "\n");
0049
0050     intel_gt_pm_get(engine->gt);
0051
0052     /* Discard stale context state from across idling */
0053     ce = engine->kernel_context;
0054     if (ce) {
0055         GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, &ce->flags));
0056
0057         /* Flush all pending HW writes before we touch the context */
0058         while (unlikely(intel_context_inflight(ce)))
0059             intel_engine_flush_submission(engine);
0060
0061         /* First poison the image to verify we never fully trust it */
0062         dbg_poison_ce(ce);
0063
0064         /* Scrub the context image after our loss of control */
0065         ce->ops->reset(ce);
0066
0067         CE_TRACE(ce, "reset { seqno:%x, *hwsp:%x, ring:%x }\n",
0068              ce->timeline->seqno,
0069              READ_ONCE(*ce->timeline->hwsp_seqno),
0070              ce->ring->emit);
0071         GEM_BUG_ON(ce->timeline->seqno !=
0072                READ_ONCE(*ce->timeline->hwsp_seqno));
0073     }
0074
0075     if (engine->unpark)
0076         engine->unpark(engine);
0077
0078     intel_breadcrumbs_unpark(engine->breadcrumbs);
0079     intel_engine_unpark_heartbeat(engine);
0080     return 0;
0081 }
0082
0083 static void duration(struct dma_fence *fence, struct dma_fence_cb *cb)
0084 {
0085     struct i915_request *rq = to_request(fence);
0086
0087     ewma__engine_latency_add(&rq->engine->latency,
0088                  ktime_us_delta(rq->fence.timestamp,
0089                         rq->duration.emitted));
0090 }
0091
0092 static void
0093 __queue_and_release_pm(struct i915_request *rq,
0094                struct intel_timeline *tl,
0095                struct intel_engine_cs *engine)
0096 {
0097     struct intel_gt_timelines *timelines = &engine->gt->timelines;
0098
0099     ENGINE_TRACE(engine, "parking\n");
0100
0101     /*
0102      * We have to serialise all potential retirement paths with our
0103      * submission, as we don't want to underflow either the
0104      * engine->wakeref.counter or our timeline->active_count.
0105      *
0106      * Equally, we cannot allow a new submission to start until
0107      * after we finish queueing, nor could we allow that submitter
0108      * to retire us before we are ready!
0109      */
0110     spin_lock(&timelines->lock);
0111
0112     /* Let intel_gt_retire_requests() retire us (acquired under lock) */
0113     if (!atomic_fetch_inc(&tl->active_count))
0114         list_add_tail(&tl->link, &timelines->active_list);
0115
0116     /* Hand the request over to HW and so engine_retire() */
0117     __i915_request_queue_bh(rq);
0118
0119     /* Let new submissions commence (and maybe retire this timeline) */
0120     __intel_wakeref_defer_park(&engine->wakeref);
0121
0122     spin_unlock(&timelines->lock);
0123 }
0124
0125 static bool switch_to_kernel_context(struct intel_engine_cs *engine)
0126 {
0127     struct intel_context *ce = engine->kernel_context;
0128     struct i915_request *rq;
0129     bool result = true;
0130
0131     /*
0132      * This is execlist specific behaviour intended to ensure the GPU is
0133      * idle by switching to a known 'safe' context. With GuC submission, the
0134      * same idle guarantee is achieved by other means (disabling
0135      * scheduling). Further, switching to a 'safe' context has no effect
0136      * with GuC submission as the scheduler can just switch back again.
0137      *
0138      * FIXME: Move this backend scheduler specific behaviour into the
0139      * scheduler backend.
0140      */
0141     if (intel_engine_uses_guc(engine))
0142         return true;
0143
0144     /* GPU is pointing to the void, as good as in the kernel context. */
0145     if (intel_gt_is_wedged(engine->gt))
0146         return true;
0147
0148     GEM_BUG_ON(!intel_context_is_barrier(ce));
0149     GEM_BUG_ON(ce->timeline->hwsp_ggtt != engine->status_page.vma);
0150
0151     /* Already inside the kernel context, safe to power down. */
0152     if (engine->wakeref_serial == engine->serial)
0153         return true;
0154
0155     /*
0156      * Note, we do this without taking the timeline->mutex. We cannot
0157      * as we may be called while retiring the kernel context and so
0158      * already underneath the timeline->mutex. Instead we rely on the
0159      * exclusive property of the __engine_park that prevents anyone
0160      * else from creating a request on this engine. This also requires
0161      * that the ring is empty and we avoid any waits while constructing
0162      * the context, as they assume protection by the timeline->mutex.
0163      * This should hold true as we can only park the engine after
0164      * retiring the last request, thus all rings should be empty and
0165      * all timelines idle.
0166      *
0167      * For unlocking, there are 2 other parties and the GPU who have a
0168      * stake here.
0169      *
0170      * A new gpu user will be waiting on the engine-pm to start their
0171      * engine_unpark. New waiters are predicated on engine->wakeref.count
0172      * and so intel_wakeref_defer_park() acts like a mutex_unlock of the
0173      * engine->wakeref.
0174      *
0175      * The other party is intel_gt_retire_requests(), which is walking the
0176      * list of active timelines looking for completions. Meanwhile as soon
0177      * as we call __i915_request_queue(), the GPU may complete our request.
0178      * Ergo, if we put ourselves on the timelines.active_list
0179      * (se intel_timeline_enter()) before we increment the
0180      * engine->wakeref.count, we may see the request completion and retire
0181      * it causing an underflow of the engine->wakeref.
0182      */
0183     set_bit(CONTEXT_IS_PARKING, &ce->flags);
0184     GEM_BUG_ON(atomic_read(&ce->timeline->active_count) < 0);
0185
0186     rq = __i915_request_create(ce, GFP_NOWAIT);
0187     if (IS_ERR(rq))
0188         /* Context switch failed, hope for the best! Maybe reset? */
0189         goto out_unlock;
0190
0191     /* Check again on the next retirement. */
0192     engine->wakeref_serial = engine->serial + 1;
0193     i915_request_add_active_barriers(rq);
0194
0195     /* Install ourselves as a preemption barrier */
0196     rq->sched.attr.priority = I915_PRIORITY_BARRIER;
0197     if (likely(!__i915_request_commit(rq))) { /* engine should be idle! */
0198         /*
0199          * Use an interrupt for precise measurement of duration,
0200          * otherwise we rely on someone else retiring all the requests
0201          * which may delay the signaling (i.e. we will likely wait
0202          * until the background request retirement running every
0203          * second or two).
0204          */
0205         BUILD_BUG_ON(sizeof(rq->duration) > sizeof(rq->submitq));
0206         dma_fence_add_callback(&rq->fence, &rq->duration.cb, duration);
0207         rq->duration.emitted = ktime_get();
0208     }
0209
0210     /* Expose ourselves to the world */
0211     __queue_and_release_pm(rq, ce->timeline, engine);
0212
0213     result = false;
0214 out_unlock:
0215     clear_bit(CONTEXT_IS_PARKING, &ce->flags);
0216     return result;
0217 }
0218
0219 static void call_idle_barriers(struct intel_engine_cs *engine)
0220 {
0221     struct llist_node *node, *next;
0222
0223     llist_for_each_safe(node, next, llist_del_all(&engine->barrier_tasks)) {
0224         struct dma_fence_cb *cb =
0225             container_of((struct list_head *)node,
0226                      typeof(*cb), node);
0227
0228         cb->func(ERR_PTR(-EAGAIN), cb);
0229     }
0230 }
0231
0232 static int __engine_park(struct intel_wakeref *wf)
0233 {
0234     struct intel_engine_cs *engine =
0235         container_of(wf, typeof(*engine), wakeref);
0236
0237     engine->saturated = 0;
0238
0239     /*
0240      * If one and only one request is completed between pm events,
0241      * we know that we are inside the kernel context and it is
0242      * safe to power down. (We are paranoid in case that runtime
0243      * suspend causes corruption to the active context image, and
0244      * want to avoid that impacting userspace.)
0245      */
0246     if (!switch_to_kernel_context(engine))
0247         return -EBUSY;
0248
0249     ENGINE_TRACE(engine, "parked\n");
0250
0251     call_idle_barriers(engine); /* cleanup after wedging */
0252
0253     intel_engine_park_heartbeat(engine);
0254     intel_breadcrumbs_park(engine->breadcrumbs);
0255
0256     /* Must be reset upon idling, or we may miss the busy wakeup. */
0257     GEM_BUG_ON(engine->sched_engine->queue_priority_hint != INT_MIN);
0258
0259     if (engine->park)
0260         engine->park(engine);
0261
0262     /* While gt calls i915_vma_parked(), we have to break the lock cycle */
0263     intel_gt_pm_put_async(engine->gt);
0264     return 0;
0265 }
0266
0267 static const struct intel_wakeref_ops wf_ops = {
0268     .get = __engine_unpark,
0269     .put = __engine_park,
0270 };
0271
0272 void intel_engine_init__pm(struct intel_engine_cs *engine)
0273 {
0274     struct intel_runtime_pm *rpm = engine->uncore->rpm;
0275
0276     intel_wakeref_init(&engine->wakeref, rpm, &wf_ops);
0277     intel_engine_init_heartbeat(engine);
0278 }
0279
0280 /**
0281  * intel_engine_reset_pinned_contexts - Reset the pinned contexts of
0282  * an engine.
0283  * @engine: The engine whose pinned contexts we want to reset.
0284  *
0285  * Typically the pinned context LMEM images lose or get their content
0286  * corrupted on suspend. This function resets their images.
0287  */
0288 void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine)
0289 {
0290     struct intel_context *ce;
0291
0292     list_for_each_entry(ce, &engine->pinned_contexts_list,
0293                 pinned_contexts_link) {
0294         /* kernel context gets reset at __engine_unpark() */
0295         if (ce == engine->kernel_context)
0296             continue;
0297
0298         dbg_poison_ce(ce);
0299         ce->ops->reset(ce);
0300     }
0301 }
0302
0303 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
0304 #include "selftest_engine_pm.c"
0305 #endif