i915/gt/intel_engine_cs.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2016 Intel Corporation
0004  */
0005
0006 #include <linux/string_helpers.h>
0007
0008 #include <drm/drm_print.h>
0009
0010 #include "gem/i915_gem_context.h"
0011 #include "gem/i915_gem_internal.h"
0012 #include "gt/intel_gt_regs.h"
0013
0014 #include "i915_cmd_parser.h"
0015 #include "i915_drv.h"
0016 #include "intel_breadcrumbs.h"
0017 #include "intel_context.h"
0018 #include "intel_engine.h"
0019 #include "intel_engine_pm.h"
0020 #include "intel_engine_regs.h"
0021 #include "intel_engine_user.h"
0022 #include "intel_execlists_submission.h"
0023 #include "intel_gt.h"
0024 #include "intel_gt_mcr.h"
0025 #include "intel_gt_pm.h"
0026 #include "intel_gt_requests.h"
0027 #include "intel_lrc.h"
0028 #include "intel_lrc_reg.h"
0029 #include "intel_reset.h"
0030 #include "intel_ring.h"
0031 #include "uc/intel_guc_submission.h"
0032
0033 /* Haswell does have the CXT_SIZE register however it does not appear to be
0034  * valid. Now, docs explain in dwords what is in the context object. The full
0035  * size is 70720 bytes, however, the power context and execlist context will
0036  * never be saved (power context is stored elsewhere, and execlists don't work
0037  * on HSW) - so the final size, including the extra state required for the
0038  * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
0039  */
0040 #define HSW_CXT_TOTAL_SIZE      (17 * PAGE_SIZE)
0041
0042 #define DEFAULT_LR_CONTEXT_RENDER_SIZE  (22 * PAGE_SIZE)
0043 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
0044 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
0045 #define GEN11_LR_CONTEXT_RENDER_SIZE    (14 * PAGE_SIZE)
0046
0047 #define GEN8_LR_CONTEXT_OTHER_SIZE  ( 2 * PAGE_SIZE)
0048
0049 #define MAX_MMIO_BASES 3
0050 struct engine_info {
0051     u8 class;
0052     u8 instance;
0053     /* mmio bases table *must* be sorted in reverse graphics_ver order */
0054     struct engine_mmio_base {
0055         u32 graphics_ver : 8;
0056         u32 base : 24;
0057     } mmio_bases[MAX_MMIO_BASES];
0058 };
0059
0060 static const struct engine_info intel_engines[] = {
0061     [RCS0] = {
0062         .class = RENDER_CLASS,
0063         .instance = 0,
0064         .mmio_bases = {
0065             { .graphics_ver = 1, .base = RENDER_RING_BASE }
0066         },
0067     },
0068     [BCS0] = {
0069         .class = COPY_ENGINE_CLASS,
0070         .instance = 0,
0071         .mmio_bases = {
0072             { .graphics_ver = 6, .base = BLT_RING_BASE }
0073         },
0074     },
0075     [BCS1] = {
0076         .class = COPY_ENGINE_CLASS,
0077         .instance = 1,
0078         .mmio_bases = {
0079             { .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
0080         },
0081     },
0082     [BCS2] = {
0083         .class = COPY_ENGINE_CLASS,
0084         .instance = 2,
0085         .mmio_bases = {
0086             { .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
0087         },
0088     },
0089     [BCS3] = {
0090         .class = COPY_ENGINE_CLASS,
0091         .instance = 3,
0092         .mmio_bases = {
0093             { .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
0094         },
0095     },
0096     [BCS4] = {
0097         .class = COPY_ENGINE_CLASS,
0098         .instance = 4,
0099         .mmio_bases = {
0100             { .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
0101         },
0102     },
0103     [BCS5] = {
0104         .class = COPY_ENGINE_CLASS,
0105         .instance = 5,
0106         .mmio_bases = {
0107             { .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
0108         },
0109     },
0110     [BCS6] = {
0111         .class = COPY_ENGINE_CLASS,
0112         .instance = 6,
0113         .mmio_bases = {
0114             { .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
0115         },
0116     },
0117     [BCS7] = {
0118         .class = COPY_ENGINE_CLASS,
0119         .instance = 7,
0120         .mmio_bases = {
0121             { .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
0122         },
0123     },
0124     [BCS8] = {
0125         .class = COPY_ENGINE_CLASS,
0126         .instance = 8,
0127         .mmio_bases = {
0128             { .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
0129         },
0130     },
0131     [VCS0] = {
0132         .class = VIDEO_DECODE_CLASS,
0133         .instance = 0,
0134         .mmio_bases = {
0135             { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
0136             { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
0137             { .graphics_ver = 4, .base = BSD_RING_BASE }
0138         },
0139     },
0140     [VCS1] = {
0141         .class = VIDEO_DECODE_CLASS,
0142         .instance = 1,
0143         .mmio_bases = {
0144             { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
0145             { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
0146         },
0147     },
0148     [VCS2] = {
0149         .class = VIDEO_DECODE_CLASS,
0150         .instance = 2,
0151         .mmio_bases = {
0152             { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
0153         },
0154     },
0155     [VCS3] = {
0156         .class = VIDEO_DECODE_CLASS,
0157         .instance = 3,
0158         .mmio_bases = {
0159             { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
0160         },
0161     },
0162     [VCS4] = {
0163         .class = VIDEO_DECODE_CLASS,
0164         .instance = 4,
0165         .mmio_bases = {
0166             { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE }
0167         },
0168     },
0169     [VCS5] = {
0170         .class = VIDEO_DECODE_CLASS,
0171         .instance = 5,
0172         .mmio_bases = {
0173             { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
0174         },
0175     },
0176     [VCS6] = {
0177         .class = VIDEO_DECODE_CLASS,
0178         .instance = 6,
0179         .mmio_bases = {
0180             { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
0181         },
0182     },
0183     [VCS7] = {
0184         .class = VIDEO_DECODE_CLASS,
0185         .instance = 7,
0186         .mmio_bases = {
0187             { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
0188         },
0189     },
0190     [VECS0] = {
0191         .class = VIDEO_ENHANCEMENT_CLASS,
0192         .instance = 0,
0193         .mmio_bases = {
0194             { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
0195             { .graphics_ver = 7, .base = VEBOX_RING_BASE }
0196         },
0197     },
0198     [VECS1] = {
0199         .class = VIDEO_ENHANCEMENT_CLASS,
0200         .instance = 1,
0201         .mmio_bases = {
0202             { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
0203         },
0204     },
0205     [VECS2] = {
0206         .class = VIDEO_ENHANCEMENT_CLASS,
0207         .instance = 2,
0208         .mmio_bases = {
0209             { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
0210         },
0211     },
0212     [VECS3] = {
0213         .class = VIDEO_ENHANCEMENT_CLASS,
0214         .instance = 3,
0215         .mmio_bases = {
0216             { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
0217         },
0218     },
0219     [CCS0] = {
0220         .class = COMPUTE_CLASS,
0221         .instance = 0,
0222         .mmio_bases = {
0223             { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
0224         }
0225     },
0226     [CCS1] = {
0227         .class = COMPUTE_CLASS,
0228         .instance = 1,
0229         .mmio_bases = {
0230             { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
0231         }
0232     },
0233     [CCS2] = {
0234         .class = COMPUTE_CLASS,
0235         .instance = 2,
0236         .mmio_bases = {
0237             { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
0238         }
0239     },
0240     [CCS3] = {
0241         .class = COMPUTE_CLASS,
0242         .instance = 3,
0243         .mmio_bases = {
0244             { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
0245         }
0246     },
0247 };
0248
0249 /**
0250  * intel_engine_context_size() - return the size of the context for an engine
0251  * @gt: the gt
0252  * @class: engine class
0253  *
0254  * Each engine class may require a different amount of space for a context
0255  * image.
0256  *
0257  * Return: size (in bytes) of an engine class specific context image
0258  *
0259  * Note: this size includes the HWSP, which is part of the context image
0260  * in LRC mode, but does not include the "shared data page" used with
0261  * GuC submission. The caller should account for this if using the GuC.
0262  */
0263 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
0264 {
0265     struct intel_uncore *uncore = gt->uncore;
0266     u32 cxt_size;
0267
0268     BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
0269
0270     switch (class) {
0271     case COMPUTE_CLASS:
0272         fallthrough;
0273     case RENDER_CLASS:
0274         switch (GRAPHICS_VER(gt->i915)) {
0275         default:
0276             MISSING_CASE(GRAPHICS_VER(gt->i915));
0277             return DEFAULT_LR_CONTEXT_RENDER_SIZE;
0278         case 12:
0279         case 11:
0280             return GEN11_LR_CONTEXT_RENDER_SIZE;
0281         case 9:
0282             return GEN9_LR_CONTEXT_RENDER_SIZE;
0283         case 8:
0284             return GEN8_LR_CONTEXT_RENDER_SIZE;
0285         case 7:
0286             if (IS_HASWELL(gt->i915))
0287                 return HSW_CXT_TOTAL_SIZE;
0288
0289             cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
0290             return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
0291                     PAGE_SIZE);
0292         case 6:
0293             cxt_size = intel_uncore_read(uncore, CXT_SIZE);
0294             return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
0295                     PAGE_SIZE);
0296         case 5:
0297         case 4:
0298             /*
0299              * There is a discrepancy here between the size reported
0300              * by the register and the size of the context layout
0301              * in the docs. Both are described as authorative!
0302              *
0303              * The discrepancy is on the order of a few cachelines,
0304              * but the total is under one page (4k), which is our
0305              * minimum allocation anyway so it should all come
0306              * out in the wash.
0307              */
0308             cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
0309             drm_dbg(&gt->i915->drm,
0310                 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
0311                 GRAPHICS_VER(gt->i915), cxt_size * 64,
0312                 cxt_size - 1);
0313             return round_up(cxt_size * 64, PAGE_SIZE);
0314         case 3:
0315         case 2:
0316         /* For the special day when i810 gets merged. */
0317         case 1:
0318             return 0;
0319         }
0320         break;
0321     default:
0322         MISSING_CASE(class);
0323         fallthrough;
0324     case VIDEO_DECODE_CLASS:
0325     case VIDEO_ENHANCEMENT_CLASS:
0326     case COPY_ENGINE_CLASS:
0327         if (GRAPHICS_VER(gt->i915) < 8)
0328             return 0;
0329         return GEN8_LR_CONTEXT_OTHER_SIZE;
0330     }
0331 }
0332
0333 static u32 __engine_mmio_base(struct drm_i915_private *i915,
0334                   const struct engine_mmio_base *bases)
0335 {
0336     int i;
0337
0338     for (i = 0; i < MAX_MMIO_BASES; i++)
0339         if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
0340             break;
0341
0342     GEM_BUG_ON(i == MAX_MMIO_BASES);
0343     GEM_BUG_ON(!bases[i].base);
0344
0345     return bases[i].base;
0346 }
0347
0348 static void __sprint_engine_name(struct intel_engine_cs *engine)
0349 {
0350     /*
0351      * Before we know what the uABI name for this engine will be,
0352      * we still would like to keep track of this engine in the debug logs.
0353      * We throw in a ' here as a reminder that this isn't its final name.
0354      */
0355     GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
0356                  intel_engine_class_repr(engine->class),
0357                  engine->instance) >= sizeof(engine->name));
0358 }
0359
0360 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
0361 {
0362     /*
0363      * Though they added more rings on g4x/ilk, they did not add
0364      * per-engine HWSTAM until gen6.
0365      */
0366     if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
0367         return;
0368
0369     if (GRAPHICS_VER(engine->i915) >= 3)
0370         ENGINE_WRITE(engine, RING_HWSTAM, mask);
0371     else
0372         ENGINE_WRITE16(engine, RING_HWSTAM, mask);
0373 }
0374
0375 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
0376 {
0377     /* Mask off all writes into the unknown HWSP */
0378     intel_engine_set_hwsp_writemask(engine, ~0u);
0379 }
0380
0381 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
0382 {
0383     GEM_DEBUG_WARN_ON(iir);
0384 }
0385
0386 static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
0387 {
0388     u32 reset_domain;
0389
0390     if (ver >= 11) {
0391         static const u32 engine_reset_domains[] = {
0392             [RCS0]  = GEN11_GRDOM_RENDER,
0393             [BCS0]  = GEN11_GRDOM_BLT,
0394             [BCS1]  = XEHPC_GRDOM_BLT1,
0395             [BCS2]  = XEHPC_GRDOM_BLT2,
0396             [BCS3]  = XEHPC_GRDOM_BLT3,
0397             [BCS4]  = XEHPC_GRDOM_BLT4,
0398             [BCS5]  = XEHPC_GRDOM_BLT5,
0399             [BCS6]  = XEHPC_GRDOM_BLT6,
0400             [BCS7]  = XEHPC_GRDOM_BLT7,
0401             [BCS8]  = XEHPC_GRDOM_BLT8,
0402             [VCS0]  = GEN11_GRDOM_MEDIA,
0403             [VCS1]  = GEN11_GRDOM_MEDIA2,
0404             [VCS2]  = GEN11_GRDOM_MEDIA3,
0405             [VCS3]  = GEN11_GRDOM_MEDIA4,
0406             [VCS4]  = GEN11_GRDOM_MEDIA5,
0407             [VCS5]  = GEN11_GRDOM_MEDIA6,
0408             [VCS6]  = GEN11_GRDOM_MEDIA7,
0409             [VCS7]  = GEN11_GRDOM_MEDIA8,
0410             [VECS0] = GEN11_GRDOM_VECS,
0411             [VECS1] = GEN11_GRDOM_VECS2,
0412             [VECS2] = GEN11_GRDOM_VECS3,
0413             [VECS3] = GEN11_GRDOM_VECS4,
0414             [CCS0]  = GEN11_GRDOM_RENDER,
0415             [CCS1]  = GEN11_GRDOM_RENDER,
0416             [CCS2]  = GEN11_GRDOM_RENDER,
0417             [CCS3]  = GEN11_GRDOM_RENDER,
0418         };
0419         GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
0420                !engine_reset_domains[id]);
0421         reset_domain = engine_reset_domains[id];
0422     } else {
0423         static const u32 engine_reset_domains[] = {
0424             [RCS0]  = GEN6_GRDOM_RENDER,
0425             [BCS0]  = GEN6_GRDOM_BLT,
0426             [VCS0]  = GEN6_GRDOM_MEDIA,
0427             [VCS1]  = GEN8_GRDOM_MEDIA2,
0428             [VECS0] = GEN6_GRDOM_VECS,
0429         };
0430         GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
0431                !engine_reset_domains[id]);
0432         reset_domain = engine_reset_domains[id];
0433     }
0434
0435     return reset_domain;
0436 }
0437
0438 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
0439                   u8 logical_instance)
0440 {
0441     const struct engine_info *info = &intel_engines[id];
0442     struct drm_i915_private *i915 = gt->i915;
0443     struct intel_engine_cs *engine;
0444     u8 guc_class;
0445
0446     BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
0447     BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
0448     BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
0449     BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
0450
0451     if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
0452         return -EINVAL;
0453
0454     if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
0455         return -EINVAL;
0456
0457     if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
0458         return -EINVAL;
0459
0460     if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
0461         return -EINVAL;
0462
0463     engine = kzalloc(sizeof(*engine), GFP_KERNEL);
0464     if (!engine)
0465         return -ENOMEM;
0466
0467     BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
0468
0469     INIT_LIST_HEAD(&engine->pinned_contexts_list);
0470     engine->id = id;
0471     engine->legacy_idx = INVALID_ENGINE;
0472     engine->mask = BIT(id);
0473     engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),
0474                         id);
0475     engine->i915 = i915;
0476     engine->gt = gt;
0477     engine->uncore = gt->uncore;
0478     guc_class = engine_class_to_guc_class(info->class);
0479     engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
0480     engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
0481
0482     engine->irq_handler = nop_irq_handler;
0483
0484     engine->class = info->class;
0485     engine->instance = info->instance;
0486     engine->logical_mask = BIT(logical_instance);
0487     __sprint_engine_name(engine);
0488
0489     engine->props.heartbeat_interval_ms =
0490         CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
0491     engine->props.max_busywait_duration_ns =
0492         CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
0493     engine->props.preempt_timeout_ms =
0494         CONFIG_DRM_I915_PREEMPT_TIMEOUT;
0495     engine->props.stop_timeout_ms =
0496         CONFIG_DRM_I915_STOP_TIMEOUT;
0497     engine->props.timeslice_duration_ms =
0498         CONFIG_DRM_I915_TIMESLICE_DURATION;
0499
0500     /* Override to uninterruptible for OpenCL workloads. */
0501     if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
0502         engine->props.preempt_timeout_ms = 0;
0503
0504     if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
0505          __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
0506          engine->class == RENDER_CLASS)
0507         engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
0508
0509     /* features common between engines sharing EUs */
0510     if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
0511         engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
0512         engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
0513     }
0514
0515     engine->defaults = engine->props; /* never to change again */
0516
0517     engine->context_size = intel_engine_context_size(gt, engine->class);
0518     if (WARN_ON(engine->context_size > BIT(20)))
0519         engine->context_size = 0;
0520     if (engine->context_size)
0521         DRIVER_CAPS(i915)->has_logical_contexts = true;
0522
0523     ewma__engine_latency_init(&engine->latency);
0524     seqcount_init(&engine->stats.execlists.lock);
0525
0526     ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
0527
0528     /* Scrub mmio state on takeover */
0529     intel_engine_sanitize_mmio(engine);
0530
0531     gt->engine_class[info->class][info->instance] = engine;
0532     gt->engine[id] = engine;
0533
0534     return 0;
0535 }
0536
0537 static void __setup_engine_capabilities(struct intel_engine_cs *engine)
0538 {
0539     struct drm_i915_private *i915 = engine->i915;
0540
0541     if (engine->class == VIDEO_DECODE_CLASS) {
0542         /*
0543          * HEVC support is present on first engine instance
0544          * before Gen11 and on all instances afterwards.
0545          */
0546         if (GRAPHICS_VER(i915) >= 11 ||
0547             (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
0548             engine->uabi_capabilities |=
0549                 I915_VIDEO_CLASS_CAPABILITY_HEVC;
0550
0551         /*
0552          * SFC block is present only on even logical engine
0553          * instances.
0554          */
0555         if ((GRAPHICS_VER(i915) >= 11 &&
0556              (engine->gt->info.vdbox_sfc_access &
0557               BIT(engine->instance))) ||
0558             (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
0559             engine->uabi_capabilities |=
0560                 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
0561     } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
0562         if (GRAPHICS_VER(i915) >= 9 &&
0563             engine->gt->info.sfc_mask & BIT(engine->instance))
0564             engine->uabi_capabilities |=
0565                 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
0566     }
0567 }
0568
0569 static void intel_setup_engine_capabilities(struct intel_gt *gt)
0570 {
0571     struct intel_engine_cs *engine;
0572     enum intel_engine_id id;
0573
0574     for_each_engine(engine, gt, id)
0575         __setup_engine_capabilities(engine);
0576 }
0577
0578 /**
0579  * intel_engines_release() - free the resources allocated for Command Streamers
0580  * @gt: pointer to struct intel_gt
0581  */
0582 void intel_engines_release(struct intel_gt *gt)
0583 {
0584     struct intel_engine_cs *engine;
0585     enum intel_engine_id id;
0586
0587     /*
0588      * Before we release the resources held by engine, we must be certain
0589      * that the HW is no longer accessing them -- having the GPU scribble
0590      * to or read from a page being used for something else causes no end
0591      * of fun.
0592      *
0593      * The GPU should be reset by this point, but assume the worst just
0594      * in case we aborted before completely initialising the engines.
0595      */
0596     GEM_BUG_ON(intel_gt_pm_is_awake(gt));
0597     if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
0598         __intel_gt_reset(gt, ALL_ENGINES);
0599
0600     /* Decouple the backend; but keep the layout for late GPU resets */
0601     for_each_engine(engine, gt, id) {
0602         if (!engine->release)
0603             continue;
0604
0605         intel_wakeref_wait_for_idle(&engine->wakeref);
0606         GEM_BUG_ON(intel_engine_pm_is_awake(engine));
0607
0608         engine->release(engine);
0609         engine->release = NULL;
0610
0611         memset(&engine->reset, 0, sizeof(engine->reset));
0612     }
0613 }
0614
0615 void intel_engine_free_request_pool(struct intel_engine_cs *engine)
0616 {
0617     if (!engine->request_pool)
0618         return;
0619
0620     kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
0621 }
0622
0623 void intel_engines_free(struct intel_gt *gt)
0624 {
0625     struct intel_engine_cs *engine;
0626     enum intel_engine_id id;
0627
0628     /* Free the requests! dma-resv keeps fences around for an eternity */
0629     rcu_barrier();
0630
0631     for_each_engine(engine, gt, id) {
0632         intel_engine_free_request_pool(engine);
0633         kfree(engine);
0634         gt->engine[id] = NULL;
0635     }
0636 }
0637
0638 static
0639 bool gen11_vdbox_has_sfc(struct intel_gt *gt,
0640              unsigned int physical_vdbox,
0641              unsigned int logical_vdbox, u16 vdbox_mask)
0642 {
0643     struct drm_i915_private *i915 = gt->i915;
0644
0645     /*
0646      * In Gen11, only even numbered logical VDBOXes are hooked
0647      * up to an SFC (Scaler & Format Converter) unit.
0648      * In Gen12, Even numbered physical instance always are connected
0649      * to an SFC. Odd numbered physical instances have SFC only if
0650      * previous even instance is fused off.
0651      *
0652      * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
0653      * in the fuse register that tells us whether a specific SFC is present.
0654      */
0655     if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
0656         return false;
0657     else if (GRAPHICS_VER(i915) == 12)
0658         return (physical_vdbox % 2 == 0) ||
0659             !(BIT(physical_vdbox - 1) & vdbox_mask);
0660     else if (GRAPHICS_VER(i915) == 11)
0661         return logical_vdbox % 2 == 0;
0662
0663     MISSING_CASE(GRAPHICS_VER(i915));
0664     return false;
0665 }
0666
0667 static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
0668 {
0669     struct drm_i915_private *i915 = gt->i915;
0670     struct intel_gt_info *info = &gt->info;
0671     int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS;
0672     unsigned long ccs_mask;
0673     unsigned int i;
0674
0675     if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
0676         return;
0677
0678     ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
0679                              ss_per_ccs);
0680     /*
0681      * If all DSS in a quadrant are fused off, the corresponding CCS
0682      * engine is not available for use.
0683      */
0684     for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) {
0685         info->engine_mask &= ~BIT(_CCS(i));
0686         drm_dbg(&i915->drm, "ccs%u fused off\n", i);
0687     }
0688 }
0689
0690 static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
0691 {
0692     struct drm_i915_private *i915 = gt->i915;
0693     struct intel_gt_info *info = &gt->info;
0694     unsigned long meml3_mask;
0695     unsigned long quad;
0696
0697     meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
0698     meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
0699
0700     /*
0701      * Link Copy engines may be fused off according to meml3_mask. Each
0702      * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
0703      */
0704     for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
0705         unsigned int instance = quad * 2 + 1;
0706         intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
0707                            _BCS(instance));
0708
0709         if (mask & info->engine_mask) {
0710             drm_dbg(&i915->drm, "bcs%u fused off\n", instance);
0711             drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1);
0712
0713             info->engine_mask &= ~mask;
0714         }
0715     }
0716 }
0717
0718 /*
0719  * Determine which engines are fused off in our particular hardware.
0720  * Note that we have a catch-22 situation where we need to be able to access
0721  * the blitter forcewake domain to read the engine fuses, but at the same time
0722  * we need to know which engines are available on the system to know which
0723  * forcewake domains are present. We solve this by intializing the forcewake
0724  * domains based on the full engine mask in the platform capabilities before
0725  * calling this function and pruning the domains for fused-off engines
0726  * afterwards.
0727  */
0728 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
0729 {
0730     struct drm_i915_private *i915 = gt->i915;
0731     struct intel_gt_info *info = &gt->info;
0732     struct intel_uncore *uncore = gt->uncore;
0733     unsigned int logical_vdbox = 0;
0734     unsigned int i;
0735     u32 media_fuse, fuse1;
0736     u16 vdbox_mask;
0737     u16 vebox_mask;
0738
0739     info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
0740
0741     if (GRAPHICS_VER(i915) < 11)
0742         return info->engine_mask;
0743
0744     /*
0745      * On newer platforms the fusing register is called 'enable' and has
0746      * enable semantics, while on older platforms it is called 'disable'
0747      * and bits have disable semantices.
0748      */
0749     media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
0750     if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
0751         media_fuse = ~media_fuse;
0752
0753     vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
0754     vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
0755               GEN11_GT_VEBOX_DISABLE_SHIFT;
0756
0757     if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
0758         fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
0759         gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
0760     } else {
0761         gt->info.sfc_mask = ~0;
0762     }
0763
0764     for (i = 0; i < I915_MAX_VCS; i++) {
0765         if (!HAS_ENGINE(gt, _VCS(i))) {
0766             vdbox_mask &= ~BIT(i);
0767             continue;
0768         }
0769
0770         if (!(BIT(i) & vdbox_mask)) {
0771             info->engine_mask &= ~BIT(_VCS(i));
0772             drm_dbg(&i915->drm, "vcs%u fused off\n", i);
0773             continue;
0774         }
0775
0776         if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
0777             gt->info.vdbox_sfc_access |= BIT(i);
0778         logical_vdbox++;
0779     }
0780     drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
0781         vdbox_mask, VDBOX_MASK(gt));
0782     GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
0783
0784     for (i = 0; i < I915_MAX_VECS; i++) {
0785         if (!HAS_ENGINE(gt, _VECS(i))) {
0786             vebox_mask &= ~BIT(i);
0787             continue;
0788         }
0789
0790         if (!(BIT(i) & vebox_mask)) {
0791             info->engine_mask &= ~BIT(_VECS(i));
0792             drm_dbg(&i915->drm, "vecs%u fused off\n", i);
0793         }
0794     }
0795     drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
0796         vebox_mask, VEBOX_MASK(gt));
0797     GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
0798
0799     engine_mask_apply_compute_fuses(gt);
0800     engine_mask_apply_copy_fuses(gt);
0801
0802     return info->engine_mask;
0803 }
0804
0805 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids,
0806                  u8 class, const u8 *map, u8 num_instances)
0807 {
0808     int i, j;
0809     u8 current_logical_id = 0;
0810
0811     for (j = 0; j < num_instances; ++j) {
0812         for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
0813             if (!HAS_ENGINE(gt, i) ||
0814                 intel_engines[i].class != class)
0815                 continue;
0816
0817             if (intel_engines[i].instance == map[j]) {
0818                 logical_ids[intel_engines[i].instance] =
0819                     current_logical_id++;
0820                 break;
0821             }
0822         }
0823     }
0824 }
0825
0826 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class)
0827 {
0828     /*
0829      * Logical to physical mapping is needed for proper support
0830      * to split-frame feature.
0831      */
0832     if (MEDIA_VER(gt->i915) >= 11 && class == VIDEO_DECODE_CLASS) {
0833         const u8 map[] = { 0, 2, 4, 6, 1, 3, 5, 7 };
0834
0835         populate_logical_ids(gt, logical_ids, class,
0836                      map, ARRAY_SIZE(map));
0837     } else {
0838         int i;
0839         u8 map[MAX_ENGINE_INSTANCE + 1];
0840
0841         for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i)
0842             map[i] = i;
0843         populate_logical_ids(gt, logical_ids, class,
0844                      map, ARRAY_SIZE(map));
0845     }
0846 }
0847
0848 /**
0849  * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
0850  * @gt: pointer to struct intel_gt
0851  *
0852  * Return: non-zero if the initialization failed.
0853  */
0854 int intel_engines_init_mmio(struct intel_gt *gt)
0855 {
0856     struct drm_i915_private *i915 = gt->i915;
0857     const unsigned int engine_mask = init_engine_mask(gt);
0858     unsigned int mask = 0;
0859     unsigned int i, class;
0860     u8 logical_ids[MAX_ENGINE_INSTANCE + 1];
0861     int err;
0862
0863     drm_WARN_ON(&i915->drm, engine_mask == 0);
0864     drm_WARN_ON(&i915->drm, engine_mask &
0865             GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
0866
0867     if (i915_inject_probe_failure(i915))
0868         return -ENODEV;
0869
0870     for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) {
0871         setup_logical_ids(gt, logical_ids, class);
0872
0873         for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
0874             u8 instance = intel_engines[i].instance;
0875
0876             if (intel_engines[i].class != class ||
0877                 !HAS_ENGINE(gt, i))
0878                 continue;
0879
0880             err = intel_engine_setup(gt, i,
0881                          logical_ids[instance]);
0882             if (err)
0883                 goto cleanup;
0884
0885             mask |= BIT(i);
0886         }
0887     }
0888
0889     /*
0890      * Catch failures to update intel_engines table when the new engines
0891      * are added to the driver by a warning and disabling the forgotten
0892      * engines.
0893      */
0894     if (drm_WARN_ON(&i915->drm, mask != engine_mask))
0895         gt->info.engine_mask = mask;
0896
0897     gt->info.num_engines = hweight32(mask);
0898
0899     intel_gt_check_and_clear_faults(gt);
0900
0901     intel_setup_engine_capabilities(gt);
0902
0903     intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
0904
0905     return 0;
0906
0907 cleanup:
0908     intel_engines_free(gt);
0909     return err;
0910 }
0911
0912 void intel_engine_init_execlists(struct intel_engine_cs *engine)
0913 {
0914     struct intel_engine_execlists * const execlists = &engine->execlists;
0915
0916     execlists->port_mask = 1;
0917     GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
0918     GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
0919
0920     memset(execlists->pending, 0, sizeof(execlists->pending));
0921     execlists->active =
0922         memset(execlists->inflight, 0, sizeof(execlists->inflight));
0923 }
0924
0925 static void cleanup_status_page(struct intel_engine_cs *engine)
0926 {
0927     struct i915_vma *vma;
0928
0929     /* Prevent writes into HWSP after returning the page to the system */
0930     intel_engine_set_hwsp_writemask(engine, ~0u);
0931
0932     vma = fetch_and_zero(&engine->status_page.vma);
0933     if (!vma)
0934         return;
0935
0936     if (!HWS_NEEDS_PHYSICAL(engine->i915))
0937         i915_vma_unpin(vma);
0938
0939     i915_gem_object_unpin_map(vma->obj);
0940     i915_gem_object_put(vma->obj);
0941 }
0942
0943 static int pin_ggtt_status_page(struct intel_engine_cs *engine,
0944                 struct i915_gem_ww_ctx *ww,
0945                 struct i915_vma *vma)
0946 {
0947     unsigned int flags;
0948
0949     if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
0950         /*
0951          * On g33, we cannot place HWS above 256MiB, so
0952          * restrict its pinning to the low mappable arena.
0953          * Though this restriction is not documented for
0954          * gen4, gen5, or byt, they also behave similarly
0955          * and hang if the HWS is placed at the top of the
0956          * GTT. To generalise, it appears that all !llc
0957          * platforms have issues with us placing the HWS
0958          * above the mappable region (even though we never
0959          * actually map it).
0960          */
0961         flags = PIN_MAPPABLE;
0962     else
0963         flags = PIN_HIGH;
0964
0965     return i915_ggtt_pin(vma, ww, 0, flags);
0966 }
0967
0968 static int init_status_page(struct intel_engine_cs *engine)
0969 {
0970     struct drm_i915_gem_object *obj;
0971     struct i915_gem_ww_ctx ww;
0972     struct i915_vma *vma;
0973     void *vaddr;
0974     int ret;
0975
0976     INIT_LIST_HEAD(&engine->status_page.timelines);
0977
0978     /*
0979      * Though the HWS register does support 36bit addresses, historically
0980      * we have had hangs and corruption reported due to wild writes if
0981      * the HWS is placed above 4G. We only allow objects to be allocated
0982      * in GFP_DMA32 for i965, and no earlier physical address users had
0983      * access to more than 4G.
0984      */
0985     obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
0986     if (IS_ERR(obj)) {
0987         drm_err(&engine->i915->drm,
0988             "Failed to allocate status page\n");
0989         return PTR_ERR(obj);
0990     }
0991
0992     i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
0993
0994     vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
0995     if (IS_ERR(vma)) {
0996         ret = PTR_ERR(vma);
0997         goto err_put;
0998     }
0999
1000     i915_gem_ww_ctx_init(&ww, true);
1001 retry:
1002     ret = i915_gem_object_lock(obj, &ww);
1003     if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))
1004         ret = pin_ggtt_status_page(engine, &ww, vma);
1005     if (ret)
1006         goto err;
1007
1008     vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1009     if (IS_ERR(vaddr)) {
1010         ret = PTR_ERR(vaddr);
1011         goto err_unpin;
1012     }
1013
1014     engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
1015     engine->status_page.vma = vma;
1016
1017 err_unpin:
1018     if (ret)
1019         i915_vma_unpin(vma);
1020 err:
1021     if (ret == -EDEADLK) {
1022         ret = i915_gem_ww_ctx_backoff(&ww);
1023         if (!ret)
1024             goto retry;
1025     }
1026     i915_gem_ww_ctx_fini(&ww);
1027 err_put:
1028     if (ret)
1029         i915_gem_object_put(obj);
1030     return ret;
1031 }
1032
1033 static int engine_setup_common(struct intel_engine_cs *engine)
1034 {
1035     int err;
1036
1037     init_llist_head(&engine->barrier_tasks);
1038
1039     err = init_status_page(engine);
1040     if (err)
1041         return err;
1042
1043     engine->breadcrumbs = intel_breadcrumbs_create(engine);
1044     if (!engine->breadcrumbs) {
1045         err = -ENOMEM;
1046         goto err_status;
1047     }
1048
1049     engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL);
1050     if (!engine->sched_engine) {
1051         err = -ENOMEM;
1052         goto err_sched_engine;
1053     }
1054     engine->sched_engine->private_data = engine;
1055
1056     err = intel_engine_init_cmd_parser(engine);
1057     if (err)
1058         goto err_cmd_parser;
1059
1060     intel_engine_init_execlists(engine);
1061     intel_engine_init__pm(engine);
1062     intel_engine_init_retire(engine);
1063
1064     /* Use the whole device by default */
1065     engine->sseu =
1066         intel_sseu_from_device_info(&engine->gt->info.sseu);
1067
1068     intel_engine_init_workarounds(engine);
1069     intel_engine_init_whitelist(engine);
1070     intel_engine_init_ctx_wa(engine);
1071
1072     if (GRAPHICS_VER(engine->i915) >= 12)
1073         engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
1074
1075     return 0;
1076
1077 err_cmd_parser:
1078     i915_sched_engine_put(engine->sched_engine);
1079 err_sched_engine:
1080     intel_breadcrumbs_put(engine->breadcrumbs);
1081 err_status:
1082     cleanup_status_page(engine);
1083     return err;
1084 }
1085
1086 struct measure_breadcrumb {
1087     struct i915_request rq;
1088     struct intel_ring ring;
1089     u32 cs[2048];
1090 };
1091
1092 static int measure_breadcrumb_dw(struct intel_context *ce)
1093 {
1094     struct intel_engine_cs *engine = ce->engine;
1095     struct measure_breadcrumb *frame;
1096     int dw;
1097
1098     GEM_BUG_ON(!engine->gt->scratch);
1099
1100     frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1101     if (!frame)
1102         return -ENOMEM;
1103
1104     frame->rq.engine = engine;
1105     frame->rq.context = ce;
1106     rcu_assign_pointer(frame->rq.timeline, ce->timeline);
1107     frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;
1108
1109     frame->ring.vaddr = frame->cs;
1110     frame->ring.size = sizeof(frame->cs);
1111     frame->ring.wrap =
1112         BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
1113     frame->ring.effective_size = frame->ring.size;
1114     intel_ring_update_space(&frame->ring);
1115     frame->rq.ring = &frame->ring;
1116
1117     mutex_lock(&ce->timeline->mutex);
1118     spin_lock_irq(&engine->sched_engine->lock);
1119
1120     dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
1121
1122     spin_unlock_irq(&engine->sched_engine->lock);
1123     mutex_unlock(&ce->timeline->mutex);
1124
1125     GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
1126
1127     kfree(frame);
1128     return dw;
1129 }
1130
1131 struct intel_context *
1132 intel_engine_create_pinned_context(struct intel_engine_cs *engine,
1133                    struct i915_address_space *vm,
1134                    unsigned int ring_size,
1135                    unsigned int hwsp,
1136                    struct lock_class_key *key,
1137                    const char *name)
1138 {
1139     struct intel_context *ce;
1140     int err;
1141
1142     ce = intel_context_create(engine);
1143     if (IS_ERR(ce))
1144         return ce;
1145
1146     __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
1147     ce->timeline = page_pack_bits(NULL, hwsp);
1148     ce->ring = NULL;
1149     ce->ring_size = ring_size;
1150
1151     i915_vm_put(ce->vm);
1152     ce->vm = i915_vm_get(vm);
1153
1154     err = intel_context_pin(ce); /* perma-pin so it is always available */
1155     if (err) {
1156         intel_context_put(ce);
1157         return ERR_PTR(err);
1158     }
1159
1160     list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
1161
1162     /*
1163      * Give our perma-pinned kernel timelines a separate lockdep class,
1164      * so that we can use them from within the normal user timelines
1165      * should we need to inject GPU operations during their request
1166      * construction.
1167      */
1168     lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
1169
1170     return ce;
1171 }
1172
1173 void intel_engine_destroy_pinned_context(struct intel_context *ce)
1174 {
1175     struct intel_engine_cs *engine = ce->engine;
1176     struct i915_vma *hwsp = engine->status_page.vma;
1177
1178     GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
1179
1180     mutex_lock(&hwsp->vm->mutex);
1181     list_del(&ce->timeline->engine_link);
1182     mutex_unlock(&hwsp->vm->mutex);
1183
1184     list_del(&ce->pinned_contexts_link);
1185     intel_context_unpin(ce);
1186     intel_context_put(ce);
1187 }
1188
1189 static struct intel_context *
1190 create_kernel_context(struct intel_engine_cs *engine)
1191 {
1192     static struct lock_class_key kernel;
1193
1194     return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
1195                           I915_GEM_HWS_SEQNO_ADDR,
1196                           &kernel, "kernel_context");
1197 }
1198
1199 /**
1200  * intel_engines_init_common - initialize cengine state which might require hw access
1201  * @engine: Engine to initialize.
1202  *
1203  * Initializes @engine@ structure members shared between legacy and execlists
1204  * submission modes which do require hardware access.
1205  *
1206  * Typcally done at later stages of submission mode specific engine setup.
1207  *
1208  * Returns zero on success or an error code on failure.
1209  */
1210 static int engine_init_common(struct intel_engine_cs *engine)
1211 {
1212     struct intel_context *ce;
1213     int ret;
1214
1215     engine->set_default_submission(engine);
1216
1217     /*
1218      * We may need to do things with the shrinker which
1219      * require us to immediately switch back to the default
1220      * context. This can cause a problem as pinning the
1221      * default context also requires GTT space which may not
1222      * be available. To avoid this we always pin the default
1223      * context.
1224      */
1225     ce = create_kernel_context(engine);
1226     if (IS_ERR(ce))
1227         return PTR_ERR(ce);
1228
1229     ret = measure_breadcrumb_dw(ce);
1230     if (ret < 0)
1231         goto err_context;
1232
1233     engine->emit_fini_breadcrumb_dw = ret;
1234     engine->kernel_context = ce;
1235
1236     return 0;
1237
1238 err_context:
1239     intel_engine_destroy_pinned_context(ce);
1240     return ret;
1241 }
1242
1243 int intel_engines_init(struct intel_gt *gt)
1244 {
1245     int (*setup)(struct intel_engine_cs *engine);
1246     struct intel_engine_cs *engine;
1247     enum intel_engine_id id;
1248     int err;
1249
1250     if (intel_uc_uses_guc_submission(&gt->uc)) {
1251         gt->submission_method = INTEL_SUBMISSION_GUC;
1252         setup = intel_guc_submission_setup;
1253     } else if (HAS_EXECLISTS(gt->i915)) {
1254         gt->submission_method = INTEL_SUBMISSION_ELSP;
1255         setup = intel_execlists_submission_setup;
1256     } else {
1257         gt->submission_method = INTEL_SUBMISSION_RING;
1258         setup = intel_ring_submission_setup;
1259     }
1260
1261     for_each_engine(engine, gt, id) {
1262         err = engine_setup_common(engine);
1263         if (err)
1264             return err;
1265
1266         err = setup(engine);
1267         if (err)
1268             return err;
1269
1270         err = engine_init_common(engine);
1271         if (err)
1272             return err;
1273
1274         intel_engine_add_user(engine);
1275     }
1276
1277     return 0;
1278 }
1279
1280 /**
1281  * intel_engines_cleanup_common - cleans up the engine state created by
1282  *                                the common initiailizers.
1283  * @engine: Engine to cleanup.
1284  *
1285  * This cleans up everything created by the common helpers.
1286  */
1287 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
1288 {
1289     GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
1290
1291     i915_sched_engine_put(engine->sched_engine);
1292     intel_breadcrumbs_put(engine->breadcrumbs);
1293
1294     intel_engine_fini_retire(engine);
1295     intel_engine_cleanup_cmd_parser(engine);
1296
1297     if (engine->default_state)
1298         fput(engine->default_state);
1299
1300     if (engine->kernel_context)
1301         intel_engine_destroy_pinned_context(engine->kernel_context);
1302
1303     GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
1304     cleanup_status_page(engine);
1305
1306     intel_wa_list_free(&engine->ctx_wa_list);
1307     intel_wa_list_free(&engine->wa_list);
1308     intel_wa_list_free(&engine->whitelist);
1309 }
1310
1311 /**
1312  * intel_engine_resume - re-initializes the HW state of the engine
1313  * @engine: Engine to resume.
1314  *
1315  * Returns zero on success or an error code on failure.
1316  */
1317 int intel_engine_resume(struct intel_engine_cs *engine)
1318 {
1319     intel_engine_apply_workarounds(engine);
1320     intel_engine_apply_whitelist(engine);
1321
1322     return engine->resume(engine);
1323 }
1324
1325 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
1326 {
1327     struct drm_i915_private *i915 = engine->i915;
1328
1329     u64 acthd;
1330
1331     if (GRAPHICS_VER(i915) >= 8)
1332         acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
1333     else if (GRAPHICS_VER(i915) >= 4)
1334         acthd = ENGINE_READ(engine, RING_ACTHD);
1335     else
1336         acthd = ENGINE_READ(engine, ACTHD);
1337
1338     return acthd;
1339 }
1340
1341 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
1342 {
1343     u64 bbaddr;
1344
1345     if (GRAPHICS_VER(engine->i915) >= 8)
1346         bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
1347     else
1348         bbaddr = ENGINE_READ(engine, RING_BBADDR);
1349
1350     return bbaddr;
1351 }
1352
1353 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
1354 {
1355     if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1356         return 0;
1357
1358     /*
1359      * If we are doing a normal GPU reset, we can take our time and allow
1360      * the engine to quiesce. We've stopped submission to the engine, and
1361      * if we wait long enough an innocent context should complete and
1362      * leave the engine idle. So they should not be caught unaware by
1363      * the forthcoming GPU reset (which usually follows the stop_cs)!
1364      */
1365     return READ_ONCE(engine->props.stop_timeout_ms);
1366 }
1367
1368 static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
1369                   int fast_timeout_us,
1370                   int slow_timeout_ms)
1371 {
1372     struct intel_uncore *uncore = engine->uncore;
1373     const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1374     int err;
1375
1376     intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1377
1378     /*
1379      * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
1380      * stopped, set ring stop bit and prefetch disable bit to halt CS
1381      */
1382     if (IS_GRAPHICS_VER(engine->i915, 11, 12))
1383         intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1384                       _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
1385
1386     err = __intel_wait_for_register_fw(engine->uncore, mode,
1387                        MODE_IDLE, MODE_IDLE,
1388                        fast_timeout_us,
1389                        slow_timeout_ms,
1390                        NULL);
1391
1392     /* A final mmio read to let GPU writes be hopefully flushed to memory */
1393     intel_uncore_posting_read_fw(uncore, mode);
1394     return err;
1395 }
1396
1397 int intel_engine_stop_cs(struct intel_engine_cs *engine)
1398 {
1399     int err = 0;
1400
1401     if (GRAPHICS_VER(engine->i915) < 3)
1402         return -ENODEV;
1403
1404     ENGINE_TRACE(engine, "\n");
1405     /*
1406      * TODO: Find out why occasionally stopping the CS times out. Seen
1407      * especially with gem_eio tests.
1408      *
1409      * Occasionally trying to stop the cs times out, but does not adversely
1410      * affect functionality. The timeout is set as a config parameter that
1411      * defaults to 100ms. In most cases the follow up operation is to wait
1412      * for pending MI_FORCE_WAKES. The assumption is that this timeout is
1413      * sufficient for any pending MI_FORCEWAKEs to complete. Once root
1414      * caused, the caller must check and handle the return from this
1415      * function.
1416      */
1417     if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
1418         ENGINE_TRACE(engine,
1419                  "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
1420                  ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
1421                  ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
1422
1423         /*
1424          * Sometimes we observe that the idle flag is not
1425          * set even though the ring is empty. So double
1426          * check before giving up.
1427          */
1428         if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
1429             (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
1430             err = -ETIMEDOUT;
1431     }
1432
1433     return err;
1434 }
1435
1436 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1437 {
1438     ENGINE_TRACE(engine, "\n");
1439
1440     ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1441 }
1442
1443 static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
1444 {
1445     static const i915_reg_t _reg[I915_NUM_ENGINES] = {
1446         [RCS0] = MSG_IDLE_CS,
1447         [BCS0] = MSG_IDLE_BCS,
1448         [VCS0] = MSG_IDLE_VCS0,
1449         [VCS1] = MSG_IDLE_VCS1,
1450         [VCS2] = MSG_IDLE_VCS2,
1451         [VCS3] = MSG_IDLE_VCS3,
1452         [VCS4] = MSG_IDLE_VCS4,
1453         [VCS5] = MSG_IDLE_VCS5,
1454         [VCS6] = MSG_IDLE_VCS6,
1455         [VCS7] = MSG_IDLE_VCS7,
1456         [VECS0] = MSG_IDLE_VECS0,
1457         [VECS1] = MSG_IDLE_VECS1,
1458         [VECS2] = MSG_IDLE_VECS2,
1459         [VECS3] = MSG_IDLE_VECS3,
1460         [CCS0] = MSG_IDLE_CS,
1461         [CCS1] = MSG_IDLE_CS,
1462         [CCS2] = MSG_IDLE_CS,
1463         [CCS3] = MSG_IDLE_CS,
1464     };
1465     u32 val;
1466
1467     if (!_reg[engine->id].reg) {
1468         drm_err(&engine->i915->drm,
1469             "MSG IDLE undefined for engine id %u\n", engine->id);
1470         return 0;
1471     }
1472
1473     val = intel_uncore_read(engine->uncore, _reg[engine->id]);
1474
1475     /* bits[29:25] & bits[13:9] >> shift */
1476     return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
1477 }
1478
1479 static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
1480 {
1481     int ret;
1482
1483     /* Ensure GPM receives fw up/down after CS is stopped */
1484     udelay(1);
1485
1486     /* Wait for forcewake request to complete in GPM */
1487     ret =  __intel_wait_for_register_fw(gt->uncore,
1488                         GEN9_PWRGT_DOMAIN_STATUS,
1489                         fw_mask, fw_mask, 5000, 0, NULL);
1490
1491     /* Ensure CS receives fw ack from GPM */
1492     udelay(1);
1493
1494     if (ret)
1495         GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
1496 }
1497
1498 /*
1499  * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
1500  * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
1501  * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
1502  * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
1503  * are concerned only with the gt reset here, we use a logical OR of pending
1504  * forcewakeups from all reset domains and then wait for them to complete by
1505  * querying PWRGT_DOMAIN_STATUS.
1506  */
1507 void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
1508 {
1509     u32 fw_pending = __cs_pending_mi_force_wakes(engine);
1510
1511     if (fw_pending)
1512         __gpm_wait_for_fw_complete(engine->gt, fw_pending);
1513 }
1514
1515 /* NB: please notice the memset */
1516 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1517                    struct intel_instdone *instdone)
1518 {
1519     struct drm_i915_private *i915 = engine->i915;
1520     struct intel_uncore *uncore = engine->uncore;
1521     u32 mmio_base = engine->mmio_base;
1522     int slice;
1523     int subslice;
1524     int iter;
1525
1526     memset(instdone, 0, sizeof(*instdone));
1527
1528     if (GRAPHICS_VER(i915) >= 8) {
1529         instdone->instdone =
1530             intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1531
1532         if (engine->id != RCS0)
1533             return;
1534
1535         instdone->slice_common =
1536             intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1537         if (GRAPHICS_VER(i915) >= 12) {
1538             instdone->slice_common_extra[0] =
1539                 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1540             instdone->slice_common_extra[1] =
1541                 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1542         }
1543
1544         for_each_ss_steering(iter, engine->gt, slice, subslice) {
1545             instdone->sampler[slice][subslice] =
1546                 intel_gt_mcr_read(engine->gt,
1547                           GEN7_SAMPLER_INSTDONE,
1548                           slice, subslice);
1549             instdone->row[slice][subslice] =
1550                 intel_gt_mcr_read(engine->gt,
1551                           GEN7_ROW_INSTDONE,
1552                           slice, subslice);
1553         }
1554
1555         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
1556             for_each_ss_steering(iter, engine->gt, slice, subslice)
1557                 instdone->geom_svg[slice][subslice] =
1558                     intel_gt_mcr_read(engine->gt,
1559                               XEHPG_INSTDONE_GEOM_SVG,
1560                               slice, subslice);
1561         }
1562     } else if (GRAPHICS_VER(i915) >= 7) {
1563         instdone->instdone =
1564             intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1565
1566         if (engine->id != RCS0)
1567             return;
1568
1569         instdone->slice_common =
1570             intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1571         instdone->sampler[0][0] =
1572             intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1573         instdone->row[0][0] =
1574             intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1575     } else if (GRAPHICS_VER(i915) >= 4) {
1576         instdone->instdone =
1577             intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1578         if (engine->id == RCS0)
1579             /* HACK: Using the wrong struct member */
1580             instdone->slice_common =
1581                 intel_uncore_read(uncore, GEN4_INSTDONE1);
1582     } else {
1583         instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1584     }
1585 }
1586
1587 static bool ring_is_idle(struct intel_engine_cs *engine)
1588 {
1589     bool idle = true;
1590
1591     if (I915_SELFTEST_ONLY(!engine->mmio_base))
1592         return true;
1593
1594     if (!intel_engine_pm_get_if_awake(engine))
1595         return true;
1596
1597     /* First check that no commands are left in the ring */
1598     if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1599         (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1600         idle = false;
1601
1602     /* No bit for gen2, so assume the CS parser is idle */
1603     if (GRAPHICS_VER(engine->i915) > 2 &&
1604         !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1605         idle = false;
1606
1607     intel_engine_pm_put(engine);
1608
1609     return idle;
1610 }
1611
1612 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
1613 {
1614     struct tasklet_struct *t = &engine->sched_engine->tasklet;
1615
1616     if (!t->callback)
1617         return;
1618
1619     local_bh_disable();
1620     if (tasklet_trylock(t)) {
1621         /* Must wait for any GPU reset in progress. */
1622         if (__tasklet_is_enabled(t))
1623             t->callback(t);
1624         tasklet_unlock(t);
1625     }
1626     local_bh_enable();
1627
1628     /* Synchronise and wait for the tasklet on another CPU */
1629     if (sync)
1630         tasklet_unlock_wait(t);
1631 }
1632
1633 /**
1634  * intel_engine_is_idle() - Report if the engine has finished process all work
1635  * @engine: the intel_engine_cs
1636  *
1637  * Return true if there are no requests pending, nothing left to be submitted
1638  * to hardware, and that the engine is idle.
1639  */
1640 bool intel_engine_is_idle(struct intel_engine_cs *engine)
1641 {
1642     /* More white lies, if wedged, hw state is inconsistent */
1643     if (intel_gt_is_wedged(engine->gt))
1644         return true;
1645
1646     if (!intel_engine_pm_is_awake(engine))
1647         return true;
1648
1649     /* Waiting to drain ELSP? */
1650     intel_synchronize_hardirq(engine->i915);
1651     intel_engine_flush_submission(engine);
1652
1653     /* ELSP is empty, but there are ready requests? E.g. after reset */
1654     if (!i915_sched_engine_is_empty(engine->sched_engine))
1655         return false;
1656
1657     /* Ring stopped? */
1658     return ring_is_idle(engine);
1659 }
1660
1661 bool intel_engines_are_idle(struct intel_gt *gt)
1662 {
1663     struct intel_engine_cs *engine;
1664     enum intel_engine_id id;
1665
1666     /*
1667      * If the driver is wedged, HW state may be very inconsistent and
1668      * report that it is still busy, even though we have stopped using it.
1669      */
1670     if (intel_gt_is_wedged(gt))
1671         return true;
1672
1673     /* Already parked (and passed an idleness test); must still be idle */
1674     if (!READ_ONCE(gt->awake))
1675         return true;
1676
1677     for_each_engine(engine, gt, id) {
1678         if (!intel_engine_is_idle(engine))
1679             return false;
1680     }
1681
1682     return true;
1683 }
1684
1685 bool intel_engine_irq_enable(struct intel_engine_cs *engine)
1686 {
1687     if (!engine->irq_enable)
1688         return false;
1689
1690     /* Caller disables interrupts */
1691     spin_lock(&engine->gt->irq_lock);
1692     engine->irq_enable(engine);
1693     spin_unlock(&engine->gt->irq_lock);
1694
1695     return true;
1696 }
1697
1698 void intel_engine_irq_disable(struct intel_engine_cs *engine)
1699 {
1700     if (!engine->irq_disable)
1701         return;
1702
1703     /* Caller disables interrupts */
1704     spin_lock(&engine->gt->irq_lock);
1705     engine->irq_disable(engine);
1706     spin_unlock(&engine->gt->irq_lock);
1707 }
1708
1709 void intel_engines_reset_default_submission(struct intel_gt *gt)
1710 {
1711     struct intel_engine_cs *engine;
1712     enum intel_engine_id id;
1713
1714     for_each_engine(engine, gt, id) {
1715         if (engine->sanitize)
1716             engine->sanitize(engine);
1717
1718         engine->set_default_submission(engine);
1719     }
1720 }
1721
1722 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1723 {
1724     switch (GRAPHICS_VER(engine->i915)) {
1725     case 2:
1726         return false; /* uses physical not virtual addresses */
1727     case 3:
1728         /* maybe only uses physical not virtual addresses */
1729         return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1730     case 4:
1731         return !IS_I965G(engine->i915); /* who knows! */
1732     case 6:
1733         return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1734     default:
1735         return true;
1736     }
1737 }
1738
1739 static struct intel_timeline *get_timeline(struct i915_request *rq)
1740 {
1741     struct intel_timeline *tl;
1742
1743     /*
1744      * Even though we are holding the engine->sched_engine->lock here, there
1745      * is no control over the submission queue per-se and we are
1746      * inspecting the active state at a random point in time, with an
1747      * unknown queue. Play safe and make sure the timeline remains valid.
1748      * (Only being used for pretty printing, one extra kref shouldn't
1749      * cause a camel stampede!)
1750      */
1751     rcu_read_lock();
1752     tl = rcu_dereference(rq->timeline);
1753     if (!kref_get_unless_zero(&tl->kref))
1754         tl = NULL;
1755     rcu_read_unlock();
1756
1757     return tl;
1758 }
1759
1760 static int print_ring(char *buf, int sz, struct i915_request *rq)
1761 {
1762     int len = 0;
1763
1764     if (!i915_request_signaled(rq)) {
1765         struct intel_timeline *tl = get_timeline(rq);
1766
1767         len = scnprintf(buf, sz,
1768                 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
1769                 i915_ggtt_offset(rq->ring->vma),
1770                 tl ? tl->hwsp_offset : 0,
1771                 hwsp_seqno(rq),
1772                 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1773                               1000 * 1000));
1774
1775         if (tl)
1776             intel_timeline_put(tl);
1777     }
1778
1779     return len;
1780 }
1781
1782 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1783 {
1784     const size_t rowsize = 8 * sizeof(u32);
1785     const void *prev = NULL;
1786     bool skip = false;
1787     size_t pos;
1788
1789     for (pos = 0; pos < len; pos += rowsize) {
1790         char line[128];
1791
1792         if (prev && !memcmp(prev, buf + pos, rowsize)) {
1793             if (!skip) {
1794                 drm_printf(m, "*\n");
1795                 skip = true;
1796             }
1797             continue;
1798         }
1799
1800         WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1801                         rowsize, sizeof(u32),
1802                         line, sizeof(line),
1803                         false) >= sizeof(line));
1804         drm_printf(m, "[%04zx] %s\n", pos, line);
1805
1806         prev = buf + pos;
1807         skip = false;
1808     }
1809 }
1810
1811 static const char *repr_timer(const struct timer_list *t)
1812 {
1813     if (!READ_ONCE(t->expires))
1814         return "inactive";
1815
1816     if (timer_pending(t))
1817         return "active";
1818
1819     return "expired";
1820 }
1821
1822 static void intel_engine_print_registers(struct intel_engine_cs *engine,
1823                      struct drm_printer *m)
1824 {
1825     struct drm_i915_private *dev_priv = engine->i915;
1826     struct intel_engine_execlists * const execlists = &engine->execlists;
1827     u64 addr;
1828
1829     if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
1830         drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1831     if (HAS_EXECLISTS(dev_priv)) {
1832         drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
1833                ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
1834         drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
1835                ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
1836     }
1837     drm_printf(m, "\tRING_START: 0x%08x\n",
1838            ENGINE_READ(engine, RING_START));
1839     drm_printf(m, "\tRING_HEAD:  0x%08x\n",
1840            ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1841     drm_printf(m, "\tRING_TAIL:  0x%08x\n",
1842            ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1843     drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
1844            ENGINE_READ(engine, RING_CTL),
1845            ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1846     if (GRAPHICS_VER(engine->i915) > 2) {
1847         drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
1848                ENGINE_READ(engine, RING_MI_MODE),
1849                ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1850     }
1851
1852     if (GRAPHICS_VER(dev_priv) >= 6) {
1853         drm_printf(m, "\tRING_IMR:   0x%08x\n",
1854                ENGINE_READ(engine, RING_IMR));
1855         drm_printf(m, "\tRING_ESR:   0x%08x\n",
1856                ENGINE_READ(engine, RING_ESR));
1857         drm_printf(m, "\tRING_EMR:   0x%08x\n",
1858                ENGINE_READ(engine, RING_EMR));
1859         drm_printf(m, "\tRING_EIR:   0x%08x\n",
1860                ENGINE_READ(engine, RING_EIR));
1861     }
1862
1863     addr = intel_engine_get_active_head(engine);
1864     drm_printf(m, "\tACTHD:  0x%08x_%08x\n",
1865            upper_32_bits(addr), lower_32_bits(addr));
1866     addr = intel_engine_get_last_batch_head(engine);
1867     drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1868            upper_32_bits(addr), lower_32_bits(addr));
1869     if (GRAPHICS_VER(dev_priv) >= 8)
1870         addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1871     else if (GRAPHICS_VER(dev_priv) >= 4)
1872         addr = ENGINE_READ(engine, RING_DMA_FADD);
1873     else
1874         addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1875     drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1876            upper_32_bits(addr), lower_32_bits(addr));
1877     if (GRAPHICS_VER(dev_priv) >= 4) {
1878         drm_printf(m, "\tIPEIR: 0x%08x\n",
1879                ENGINE_READ(engine, RING_IPEIR));
1880         drm_printf(m, "\tIPEHR: 0x%08x\n",
1881                ENGINE_READ(engine, RING_IPEHR));
1882     } else {
1883         drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1884         drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1885     }
1886
1887     if (HAS_EXECLISTS(dev_priv) && !intel_engine_uses_guc(engine)) {
1888         struct i915_request * const *port, *rq;
1889         const u32 *hws =
1890             &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1891         const u8 num_entries = execlists->csb_size;
1892         unsigned int idx;
1893         u8 read, write;
1894
1895         drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
1896                str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)),
1897                str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)),
1898                repr_timer(&engine->execlists.preempt),
1899                repr_timer(&engine->execlists.timer));
1900
1901         read = execlists->csb_head;
1902         write = READ_ONCE(*execlists->csb_write);
1903
1904         drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
1905                ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1906                ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1907                read, write, num_entries);
1908
1909         if (read >= num_entries)
1910             read = 0;
1911         if (write >= num_entries)
1912             write = 0;
1913         if (read > write)
1914             write += num_entries;
1915         while (read < write) {
1916             idx = ++read % num_entries;
1917             drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
1918                    idx, hws[idx * 2], hws[idx * 2 + 1]);
1919         }
1920
1921         i915_sched_engine_active_lock_bh(engine->sched_engine);
1922         rcu_read_lock();
1923         for (port = execlists->active; (rq = *port); port++) {
1924             char hdr[160];
1925             int len;
1926
1927             len = scnprintf(hdr, sizeof(hdr),
1928                     "\t\tActive[%d]:  ccid:%08x%s%s, ",
1929                     (int)(port - execlists->active),
1930                     rq->context->lrc.ccid,
1931                     intel_context_is_closed(rq->context) ? "!" : "",
1932                     intel_context_is_banned(rq->context) ? "*" : "");
1933             len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1934             scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1935             i915_request_show(m, rq, hdr, 0);
1936         }
1937         for (port = execlists->pending; (rq = *port); port++) {
1938             char hdr[160];
1939             int len;
1940
1941             len = scnprintf(hdr, sizeof(hdr),
1942                     "\t\tPending[%d]: ccid:%08x%s%s, ",
1943                     (int)(port - execlists->pending),
1944                     rq->context->lrc.ccid,
1945                     intel_context_is_closed(rq->context) ? "!" : "",
1946                     intel_context_is_banned(rq->context) ? "*" : "");
1947             len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1948             scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1949             i915_request_show(m, rq, hdr, 0);
1950         }
1951         rcu_read_unlock();
1952         i915_sched_engine_active_unlock_bh(engine->sched_engine);
1953     } else if (GRAPHICS_VER(dev_priv) > 6) {
1954         drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
1955                ENGINE_READ(engine, RING_PP_DIR_BASE));
1956         drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
1957                ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
1958         drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
1959                ENGINE_READ(engine, RING_PP_DIR_DCLV));
1960     }
1961 }
1962
1963 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
1964 {
1965     struct i915_vma_resource *vma_res = rq->batch_res;
1966     void *ring;
1967     int size;
1968
1969     drm_printf(m,
1970            "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
1971            rq->head, rq->postfix, rq->tail,
1972            vma_res ? upper_32_bits(vma_res->start) : ~0u,
1973            vma_res ? lower_32_bits(vma_res->start) : ~0u);
1974
1975     size = rq->tail - rq->head;
1976     if (rq->tail < rq->head)
1977         size += rq->ring->size;
1978
1979     ring = kmalloc(size, GFP_ATOMIC);
1980     if (ring) {
1981         const void *vaddr = rq->ring->vaddr;
1982         unsigned int head = rq->head;
1983         unsigned int len = 0;
1984
1985         if (rq->tail < head) {
1986             len = rq->ring->size - head;
1987             memcpy(ring, vaddr + head, len);
1988             head = 0;
1989         }
1990         memcpy(ring + len, vaddr + head, size - len);
1991
1992         hexdump(m, ring, size);
1993         kfree(ring);
1994     }
1995 }
1996
1997 static unsigned long list_count(struct list_head *list)
1998 {
1999     struct list_head *pos;
2000     unsigned long count = 0;
2001
2002     list_for_each(pos, list)
2003         count++;
2004
2005     return count;
2006 }
2007
2008 static unsigned long read_ul(void *p, size_t x)
2009 {
2010     return *(unsigned long *)(p + x);
2011 }
2012
2013 static void print_properties(struct intel_engine_cs *engine,
2014                  struct drm_printer *m)
2015 {
2016     static const struct pmap {
2017         size_t offset;
2018         const char *name;
2019     } props[] = {
2020 #define P(x) { \
2021     .offset = offsetof(typeof(engine->props), x), \
2022     .name = #x \
2023 }
2024         P(heartbeat_interval_ms),
2025         P(max_busywait_duration_ns),
2026         P(preempt_timeout_ms),
2027         P(stop_timeout_ms),
2028         P(timeslice_duration_ms),
2029
2030         {},
2031 #undef P
2032     };
2033     const struct pmap *p;
2034
2035     drm_printf(m, "\tProperties:\n");
2036     for (p = props; p->name; p++)
2037         drm_printf(m, "\t\t%s: %lu [default %lu]\n",
2038                p->name,
2039                read_ul(&engine->props, p->offset),
2040                read_ul(&engine->defaults, p->offset));
2041 }
2042
2043 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg)
2044 {
2045     struct intel_timeline *tl = get_timeline(rq);
2046
2047     i915_request_show(m, rq, msg, 0);
2048
2049     drm_printf(m, "\t\tring->start:  0x%08x\n",
2050            i915_ggtt_offset(rq->ring->vma));
2051     drm_printf(m, "\t\tring->head:   0x%08x\n",
2052            rq->ring->head);
2053     drm_printf(m, "\t\tring->tail:   0x%08x\n",
2054            rq->ring->tail);
2055     drm_printf(m, "\t\tring->emit:   0x%08x\n",
2056            rq->ring->emit);
2057     drm_printf(m, "\t\tring->space:  0x%08x\n",
2058            rq->ring->space);
2059
2060     if (tl) {
2061         drm_printf(m, "\t\tring->hwsp:   0x%08x\n",
2062                tl->hwsp_offset);
2063         intel_timeline_put(tl);
2064     }
2065
2066     print_request_ring(m, rq);
2067
2068     if (rq->context->lrc_reg_state) {
2069         drm_printf(m, "Logical Ring Context:\n");
2070         hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
2071     }
2072 }
2073
2074 void intel_engine_dump_active_requests(struct list_head *requests,
2075                        struct i915_request *hung_rq,
2076                        struct drm_printer *m)
2077 {
2078     struct i915_request *rq;
2079     const char *msg;
2080     enum i915_request_state state;
2081
2082     list_for_each_entry(rq, requests, sched.link) {
2083         if (rq == hung_rq)
2084             continue;
2085
2086         state = i915_test_request_state(rq);
2087         if (state < I915_REQUEST_QUEUED)
2088             continue;
2089
2090         if (state == I915_REQUEST_ACTIVE)
2091             msg = "\t\tactive on engine";
2092         else
2093             msg = "\t\tactive in queue";
2094
2095         engine_dump_request(rq, m, msg);
2096     }
2097 }
2098
2099 static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m)
2100 {
2101     struct i915_request *hung_rq = NULL;
2102     struct intel_context *ce;
2103     bool guc;
2104
2105     /*
2106      * No need for an engine->irq_seqno_barrier() before the seqno reads.
2107      * The GPU is still running so requests are still executing and any
2108      * hardware reads will be out of date by the time they are reported.
2109      * But the intention here is just to report an instantaneous snapshot
2110      * so that's fine.
2111      */
2112     lockdep_assert_held(&engine->sched_engine->lock);
2113
2114     drm_printf(m, "\tRequests:\n");
2115
2116     guc = intel_uc_uses_guc_submission(&engine->gt->uc);
2117     if (guc) {
2118         ce = intel_engine_get_hung_context(engine);
2119         if (ce)
2120             hung_rq = intel_context_find_active_request(ce);
2121     } else {
2122         hung_rq = intel_engine_execlist_find_hung_request(engine);
2123     }
2124
2125     if (hung_rq)
2126         engine_dump_request(hung_rq, m, "\t\thung");
2127
2128     if (guc)
2129         intel_guc_dump_active_requests(engine, hung_rq, m);
2130     else
2131         intel_engine_dump_active_requests(&engine->sched_engine->requests,
2132                           hung_rq, m);
2133 }
2134
2135 void intel_engine_dump(struct intel_engine_cs *engine,
2136                struct drm_printer *m,
2137                const char *header, ...)
2138 {
2139     struct i915_gpu_error * const error = &engine->i915->gpu_error;
2140     struct i915_request *rq;
2141     intel_wakeref_t wakeref;
2142     unsigned long flags;
2143     ktime_t dummy;
2144
2145     if (header) {
2146         va_list ap;
2147
2148         va_start(ap, header);
2149         drm_vprintf(m, header, &ap);
2150         va_end(ap);
2151     }
2152
2153     if (intel_gt_is_wedged(engine->gt))
2154         drm_printf(m, "*** WEDGED ***\n");
2155
2156     drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
2157     drm_printf(m, "\tBarriers?: %s\n",
2158            str_yes_no(!llist_empty(&engine->barrier_tasks)));
2159     drm_printf(m, "\tLatency: %luus\n",
2160            ewma__engine_latency_read(&engine->latency));
2161     if (intel_engine_supports_stats(engine))
2162         drm_printf(m, "\tRuntime: %llums\n",
2163                ktime_to_ms(intel_engine_get_busy_time(engine,
2164                                   &dummy)));
2165     drm_printf(m, "\tForcewake: %x domains, %d active\n",
2166            engine->fw_domain, READ_ONCE(engine->fw_active));
2167
2168     rcu_read_lock();
2169     rq = READ_ONCE(engine->heartbeat.systole);
2170     if (rq)
2171         drm_printf(m, "\tHeartbeat: %d ms ago\n",
2172                jiffies_to_msecs(jiffies - rq->emitted_jiffies));
2173     rcu_read_unlock();
2174     drm_printf(m, "\tReset count: %d (global %d)\n",
2175            i915_reset_engine_count(error, engine),
2176            i915_reset_count(error));
2177     print_properties(engine, m);
2178
2179     spin_lock_irqsave(&engine->sched_engine->lock, flags);
2180     engine_dump_active_requests(engine, m);
2181
2182     drm_printf(m, "\tOn hold?: %lu\n",
2183            list_count(&engine->sched_engine->hold));
2184     spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2185
2186     drm_printf(m, "\tMMIO base:  0x%08x\n", engine->mmio_base);
2187     wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
2188     if (wakeref) {
2189         intel_engine_print_registers(engine, m);
2190         intel_runtime_pm_put(engine->uncore->rpm, wakeref);
2191     } else {
2192         drm_printf(m, "\tDevice is asleep; skipping register dump\n");
2193     }
2194
2195     intel_execlists_show_requests(engine, m, i915_request_show, 8);
2196
2197     drm_printf(m, "HWSP:\n");
2198     hexdump(m, engine->status_page.addr, PAGE_SIZE);
2199
2200     drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine)));
2201
2202     intel_engine_print_breadcrumbs(engine, m);
2203 }
2204
2205 /**
2206  * intel_engine_get_busy_time() - Return current accumulated engine busyness
2207  * @engine: engine to report on
2208  * @now: monotonic timestamp of sampling
2209  *
2210  * Returns accumulated time @engine was busy since engine stats were enabled.
2211  */
2212 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
2213 {
2214     return engine->busyness(engine, now);
2215 }
2216
2217 struct intel_context *
2218 intel_engine_create_virtual(struct intel_engine_cs **siblings,
2219                 unsigned int count, unsigned long flags)
2220 {
2221     if (count == 0)
2222         return ERR_PTR(-EINVAL);
2223
2224     if (count == 1 && !(flags & FORCE_VIRTUAL))
2225         return intel_context_create(siblings[0]);
2226
2227     GEM_BUG_ON(!siblings[0]->cops->create_virtual);
2228     return siblings[0]->cops->create_virtual(siblings, count, flags);
2229 }
2230
2231 struct i915_request *
2232 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2233 {
2234     struct i915_request *request, *active = NULL;
2235
2236     /*
2237      * This search does not work in GuC submission mode. However, the GuC
2238      * will report the hanging context directly to the driver itself. So
2239      * the driver should never get here when in GuC mode.
2240      */
2241     GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc));
2242
2243     /*
2244      * We are called by the error capture, reset and to dump engine
2245      * state at random points in time. In particular, note that neither is
2246      * crucially ordered with an interrupt. After a hang, the GPU is dead
2247      * and we assume that no more writes can happen (we waited long enough
2248      * for all writes that were in transaction to be flushed) - adding an
2249      * extra delay for a recent interrupt is pointless. Hence, we do
2250      * not need an engine->irq_seqno_barrier() before the seqno reads.
2251      * At all other times, we must assume the GPU is still running, but
2252      * we only care about the snapshot of this moment.
2253      */
2254     lockdep_assert_held(&engine->sched_engine->lock);
2255
2256     rcu_read_lock();
2257     request = execlists_active(&engine->execlists);
2258     if (request) {
2259         struct intel_timeline *tl = request->context->timeline;
2260
2261         list_for_each_entry_from_reverse(request, &tl->requests, link) {
2262             if (__i915_request_is_complete(request))
2263                 break;
2264
2265             active = request;
2266         }
2267     }
2268     rcu_read_unlock();
2269     if (active)
2270         return active;
2271
2272     list_for_each_entry(request, &engine->sched_engine->requests,
2273                 sched.link) {
2274         if (i915_test_request_state(request) != I915_REQUEST_ACTIVE)
2275             continue;
2276
2277         active = request;
2278         break;
2279     }
2280
2281     return active;
2282 }
2283
2284 void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
2285 {
2286     /*
2287      * If there are any non-fused-off CCS engines, we need to enable CCS
2288      * support in the RCU_MODE register.  This only needs to be done once,
2289      * so for simplicity we'll take care of this in the RCS engine's
2290      * resume handler; since the RCS and all CCS engines belong to the
2291      * same reset domain and are reset together, this will also take care
2292      * of re-applying the setting after i915-triggered resets.
2293      */
2294     if (!CCS_MASK(engine->gt))
2295         return;
2296
2297     intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
2298                _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
2299 }
2300
2301 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2302 #include "mock_engine.c"
2303 #include "selftest_engine.c"
2304 #include "selftest_engine_cs.c"
2305 #endif