i915/gt/intel_context_sseu.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #include "i915_drv.h"
0007 #include "i915_vma.h"
0008 #include "intel_context.h"
0009 #include "intel_engine_pm.h"
0010 #include "intel_gpu_commands.h"
0011 #include "intel_lrc.h"
0012 #include "intel_lrc_reg.h"
0013 #include "intel_ring.h"
0014 #include "intel_sseu.h"
0015
0016 static int gen8_emit_rpcs_config(struct i915_request *rq,
0017                  const struct intel_context *ce,
0018                  const struct intel_sseu sseu)
0019 {
0020     u64 offset;
0021     u32 *cs;
0022
0023     cs = intel_ring_begin(rq, 4);
0024     if (IS_ERR(cs))
0025         return PTR_ERR(cs);
0026
0027     offset = i915_ggtt_offset(ce->state) +
0028          LRC_STATE_OFFSET + CTX_R_PWR_CLK_STATE * 4;
0029
0030     *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
0031     *cs++ = lower_32_bits(offset);
0032     *cs++ = upper_32_bits(offset);
0033     *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);
0034
0035     intel_ring_advance(rq, cs);
0036
0037     return 0;
0038 }
0039
0040 static int
0041 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu)
0042 {
0043     struct i915_request *rq;
0044     int ret;
0045
0046     lockdep_assert_held(&ce->pin_mutex);
0047
0048     /*
0049      * If the context is not idle, we have to submit an ordered request to
0050      * modify its context image via the kernel context (writing to our own
0051      * image, or into the registers directory, does not stick). Pristine
0052      * and idle contexts will be configured on pinning.
0053      */
0054     if (!intel_context_pin_if_active(ce))
0055         return 0;
0056
0057     rq = intel_engine_create_kernel_request(ce->engine);
0058     if (IS_ERR(rq)) {
0059         ret = PTR_ERR(rq);
0060         goto out_unpin;
0061     }
0062
0063     /* Serialise with the remote context */
0064     ret = intel_context_prepare_remote_request(ce, rq);
0065     if (ret == 0)
0066         ret = gen8_emit_rpcs_config(rq, ce, sseu);
0067
0068     i915_request_add(rq);
0069 out_unpin:
0070     intel_context_unpin(ce);
0071     return ret;
0072 }
0073
0074 int
0075 intel_context_reconfigure_sseu(struct intel_context *ce,
0076                    const struct intel_sseu sseu)
0077 {
0078     int ret;
0079
0080     GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
0081
0082     ret = intel_context_lock_pinned(ce);
0083     if (ret)
0084         return ret;
0085
0086     /* Nothing to do if unmodified. */
0087     if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
0088         goto unlock;
0089
0090     ret = gen8_modify_rpcs(ce, sseu);
0091     if (!ret)
0092         ce->sseu = sseu;
0093
0094 unlock:
0095     intel_context_unlock_pinned(ce);
0096     return ret;
0097 }