i915/gt/gen8_engine_cs.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2014 Intel Corporation
0004  */
0005
0006 #ifndef __GEN8_ENGINE_CS_H__
0007 #define __GEN8_ENGINE_CS_H__
0008
0009 #include <linux/string.h>
0010 #include <linux/types.h>
0011
0012 #include "i915_gem.h" /* GEM_BUG_ON */
0013 #include "intel_gt_regs.h"
0014 #include "intel_gpu_commands.h"
0015
0016 struct i915_request;
0017
0018 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode);
0019 int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode);
0020 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode);
0021
0022 int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode);
0023 int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode);
0024
0025 int gen8_emit_init_breadcrumb(struct i915_request *rq);
0026
0027 int gen8_emit_bb_start_noarb(struct i915_request *rq,
0028                  u64 offset, u32 len,
0029                  const unsigned int flags);
0030 int gen8_emit_bb_start(struct i915_request *rq,
0031                u64 offset, u32 len,
0032                const unsigned int flags);
0033
0034 int gen125_emit_bb_start_noarb(struct i915_request *rq,
0035                    u64 offset, u32 len,
0036                    const unsigned int flags);
0037 int gen125_emit_bb_start(struct i915_request *rq,
0038              u64 offset, u32 len,
0039              const unsigned int flags);
0040
0041 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
0042 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
0043
0044 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
0045 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
0046 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
0047
0048 u32 *gen12_emit_aux_table_inv(u32 *cs, const i915_reg_t inv_reg);
0049
0050 static inline u32 *
0051 __gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
0052 {
0053     memset(batch, 0, 6 * sizeof(u32));
0054
0055     batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
0056     batch[1] = flags1;
0057     batch[2] = offset;
0058
0059     return batch + 6;
0060 }
0061
0062 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
0063 {
0064     return __gen8_emit_pipe_control(batch, 0, flags, offset);
0065 }
0066
0067 static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
0068 {
0069     return __gen8_emit_pipe_control(batch, flags0, flags1, offset);
0070 }
0071
0072 static inline u32 *
0073 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
0074 {
0075     *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
0076     *cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
0077     *cs++ = offset;
0078     *cs++ = 0;
0079     *cs++ = value;
0080     *cs++ = 0; /* We're thrashing one extra dword. */
0081
0082     return cs;
0083 }
0084
0085 static inline u32*
0086 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
0087 {
0088     /* We're using qword write, offset should be aligned to 8 bytes. */
0089     GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
0090
0091     return __gen8_emit_write_rcs(cs,
0092                      value,
0093                      gtt_offset,
0094                      0,
0095                      flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
0096 }
0097
0098 static inline u32*
0099 gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
0100 {
0101     /* We're using qword write, offset should be aligned to 8 bytes. */
0102     GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
0103
0104     return __gen8_emit_write_rcs(cs,
0105                      value,
0106                      gtt_offset,
0107                      flags0,
0108                      flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
0109 }
0110
0111 static inline u32 *
0112 __gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
0113 {
0114     *cs++ = (MI_FLUSH_DW + 1) | flags;
0115     *cs++ = gtt_offset;
0116     *cs++ = 0;
0117     *cs++ = value;
0118
0119     return cs;
0120 }
0121
0122 static inline u32 *
0123 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
0124 {
0125     /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
0126     GEM_BUG_ON(gtt_offset & (1 << 5));
0127     /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
0128     GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
0129
0130     return __gen8_emit_flush_dw(cs,
0131                     value,
0132                     gtt_offset | MI_FLUSH_DW_USE_GTT,
0133                     flags | MI_FLUSH_DW_OP_STOREDW);
0134 }
0135
0136 #endif /* __GEN8_ENGINE_CS_H__ */