i915/gt/gen6_engine_cs.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2020 Intel Corporation
0004  */
0005
0006 #ifndef __GEN6_ENGINE_CS_H__
0007 #define __GEN6_ENGINE_CS_H__
0008
0009 #include <linux/types.h>
0010
0011 #include "intel_gpu_commands.h"
0012
0013 struct i915_request;
0014 struct intel_engine_cs;
0015
0016 int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode);
0017 int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode);
0018 int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode);
0019 u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
0020 u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
0021
0022 int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode);
0023 u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
0024 u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
0025
0026 int gen6_emit_bb_start(struct i915_request *rq,
0027                u64 offset, u32 len,
0028                unsigned int dispatch_flags);
0029 int hsw_emit_bb_start(struct i915_request *rq,
0030               u64 offset, u32 len,
0031               unsigned int dispatch_flags);
0032
0033 void gen6_irq_enable(struct intel_engine_cs *engine);
0034 void gen6_irq_disable(struct intel_engine_cs *engine);
0035
0036 void hsw_irq_enable_vecs(struct intel_engine_cs *engine);
0037 void hsw_irq_disable_vecs(struct intel_engine_cs *engine);
0038
0039 #endif /* __GEN6_ENGINE_CS_H__ */