i915/display/vlv_dsi_pll_regs.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005
0006 #ifndef __VLV_DSI_PLL_REGS_H__
0007 #define __VLV_DSI_PLL_REGS_H__
0008
0009 #include "vlv_dsi_regs.h"
0010
0011 #define MIPIO_TXESC_CLK_DIV1            _MMIO(0x160004)
0012 #define  GLK_TX_ESC_CLK_DIV1_MASK           0x3FF
0013 #define MIPIO_TXESC_CLK_DIV2            _MMIO(0x160008)
0014 #define  GLK_TX_ESC_CLK_DIV2_MASK           0x3FF
0015
0016 #define BXT_MAX_VAR_OUTPUT_KHZ          39500
0017
0018 #define BXT_MIPI_CLOCK_CTL          _MMIO(0x46090)
0019 #define  BXT_MIPI1_DIV_SHIFT            26
0020 #define  BXT_MIPI2_DIV_SHIFT            10
0021 #define  BXT_MIPI_DIV_SHIFT(port)       \
0022             _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
0023                     BXT_MIPI2_DIV_SHIFT)
0024
0025 /* TX control divider to select actual TX clock output from (8x/var) */
0026 #define  BXT_MIPI1_TX_ESCLK_SHIFT       26
0027 #define  BXT_MIPI2_TX_ESCLK_SHIFT       10
0028 #define  BXT_MIPI_TX_ESCLK_SHIFT(port)      \
0029             _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
0030                     BXT_MIPI2_TX_ESCLK_SHIFT)
0031 #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK     (0x3F << 26)
0032 #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK     (0x3F << 10)
0033 #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)    \
0034             _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
0035                     BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
0036 #define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)   \
0037         (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
0038 /* RX upper control divider to select actual RX clock output from 8x */
0039 #define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT     21
0040 #define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT     5
0041 #define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)        \
0042             _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
0043                     BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
0044 #define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK       (3 << 21)
0045 #define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK       (3 << 5)
0046 #define  BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)  \
0047             _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
0048                     BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
0049 #define  BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
0050         (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
0051 /* 8/3X divider to select the actual 8/3X clock output from 8x */
0052 #define  BXT_MIPI1_8X_BY3_SHIFT                19
0053 #define  BXT_MIPI2_8X_BY3_SHIFT                3
0054 #define  BXT_MIPI_8X_BY3_SHIFT(port)          \
0055             _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
0056                     BXT_MIPI2_8X_BY3_SHIFT)
0057 #define  BXT_MIPI1_8X_BY3_DIVIDER_MASK         (3 << 19)
0058 #define  BXT_MIPI2_8X_BY3_DIVIDER_MASK         (3 << 3)
0059 #define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)    \
0060             _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
0061                         BXT_MIPI2_8X_BY3_DIVIDER_MASK)
0062 #define  BXT_MIPI_8X_BY3_DIVIDER(port, val)    \
0063             (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
0064 /* RX lower control divider to select actual RX clock output from 8x */
0065 #define  BXT_MIPI1_RX_ESCLK_LOWER_SHIFT     16
0066 #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT     0
0067 #define  BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)        \
0068             _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
0069                     BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
0070 #define  BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK       (3 << 16)
0071 #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK       (3 << 0)
0072 #define  BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)  \
0073             _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
0074                     BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
0075 #define  BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
0076         (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
0077
0078 #define RX_DIVIDER_BIT_1_2                     0x3
0079 #define RX_DIVIDER_BIT_3_4                     0xC
0080
0081 #define BXT_DSI_PLL_CTL         _MMIO(0x161000)
0082 #define  BXT_DSI_PLL_PVD_RATIO_SHIFT    16
0083 #define  BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
0084 #define  BXT_DSI_PLL_PVD_RATIO_1    (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
0085 #define  BXT_DSIC_16X_BY1       (0 << 10)
0086 #define  BXT_DSIC_16X_BY2       (1 << 10)
0087 #define  BXT_DSIC_16X_BY3       (2 << 10)
0088 #define  BXT_DSIC_16X_BY4       (3 << 10)
0089 #define  BXT_DSIC_16X_MASK      (3 << 10)
0090 #define  BXT_DSIA_16X_BY1       (0 << 8)
0091 #define  BXT_DSIA_16X_BY2       (1 << 8)
0092 #define  BXT_DSIA_16X_BY3       (2 << 8)
0093 #define  BXT_DSIA_16X_BY4       (3 << 8)
0094 #define  BXT_DSIA_16X_MASK      (3 << 8)
0095 #define  BXT_DSI_FREQ_SEL_SHIFT     8
0096 #define  BXT_DSI_FREQ_SEL_MASK      (0xF << BXT_DSI_FREQ_SEL_SHIFT)
0097
0098 #define BXT_DSI_PLL_RATIO_MAX       0x7D
0099 #define BXT_DSI_PLL_RATIO_MIN       0x22
0100 #define GLK_DSI_PLL_RATIO_MAX       0x6F
0101 #define GLK_DSI_PLL_RATIO_MIN       0x22
0102 #define BXT_DSI_PLL_RATIO_MASK      0xFF
0103 #define BXT_REF_CLOCK_KHZ       19200
0104
0105 #define BXT_DSI_PLL_ENABLE      _MMIO(0x46080)
0106 #define  BXT_DSI_PLL_DO_ENABLE      (1 << 31)
0107 #define  BXT_DSI_PLL_LOCKED     (1 << 30)
0108
0109 #endif /* __VLV_DSI_PLL_REGS_H__ */